Abov MC96F6432Q manuals

MC96F6432Q

Brand: Abov | Category: Microcontrollers

Table of contents

Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Overview
Features
Ordering Information
Development Tools
Figure 1.2 E-PGM+(Single writer)
Figure 1.3 E-GANG4 and E-GANG6 (for Mass Production)
Block Diagram
Pin Assignment
Figure 3.2 MC96F6432Q 44MQFP-1010 Pin Assignment
Figure 3.3 MC96F6332L 32LQFP Pin Assignment
Figure 3.4 MC96F6332D 32SOP Pin Assignment
Package Diagram
Figure 4.2 44-Pin MQFP Package
Figure 4.3 32-Pin LQFP Package
Figure 4.4 32-Pin SOP Package
Figure 4.5 28-Pin SOP Package
Pin Description
Port Structures
External Interrupt I/O Port
Electrical Characteristics
A/D Converter Characteristics
Low Voltage Reset and Low Voltage Indicator Characteristics
High Internal RC Oscillator Characteristics
LCD Voltage Characteristics
DC Characteristics
AC Characteristics
SPI0/1/2 Characteristics
UART0/1 Characteristics
I2C0/1 Characteristics
Data Retention Voltage in Stop Mode
Internal Flash Rom Characteristics
Main Clock Oscillator Characteristics
Sub Clock Oscillator Characteristics
Main Oscillation Stabilization Characteristics
Operating Voltage Range
Recommended Circuit and Layout
Recommended Circuit and Layout with SMPS Power
Typical Characteristics
Figure 7.19 SUB RUN (IDD3) Current
Figure 7.21 STOP (IDD5) Current
Memory
Figure 8.1 Program Memory
Data Memory
Figure 8.3 Lower 128 Bytes RAM
XRAM Memory
Table 8-1 SFR Map Summary
Table 8-2 SFR Map Summary
Table 8-3 SFR Map
I/O Ports
Table 9-1 Port Register Map
Port Function
Interrupt Controller
External Interrupt
Interrupt Vector Table
Figure 10.3 Interrupt Sequence Flow
Effective Timing after Controlling Interrupt Bit
Multi Interrupt
Interrupt Enable Accept Timing
Interrupt Timing
Table 10-3 Interrupt Register Map
Peripheral Hardware
Table 11-1 Clock Generator Register Map
Basic Interval Timer
Table 11-2 Basic Interval Timer Register Map
Watch Dog Timer
Figure 11.4 Watch Dog Timer Block Diagram
Watch Timer
Table 11-4 Watch Timer Register Map
Timer 0
Figure 11.6 8-Bit Timer/Counter Mode for Timer 0
Figure 11.8 8-Bit PWM Mode for Timer 0
Figure 11.9 PWM Output Waveforms in PWM Mode for Timer 0
Figure 11.10 8-Bit Capture Mode for Timer 0
Figure 11.11 Input Capture Mode Operation for Timer 0
Figure 11.13 8-Bit Timer 0 Block Diagram
Table 11-6 Timer 0 Register Map
Timer 1
Figure 11.14 16-Bit Timer/Counter Mode for Timer 1
Figure 11.16 16-Bit Capture Mode for Timer 1
Figure 11.17 Input Capture Mode Operation for Timer 1
Figure 11.19 16-Bit PPG Mode for Timer 1
Figure 11.20 16-Bit PPG Mode Timming chart for Timer 1
Figure 11.21 16-Bit Timer 1 Block Diagram
Timer 2
Figure 11.22 16-Bit Timer/Counter Mode for Timer 2
Figure 11.23 16-Bit Timer/Counter 2 Example
Figure 11.24 16-Bit Capture Mode for Timer 2
Figure 11.25 Input Capture Mode Operation for Timer 2
Figure 11.27 16-Bit PPG Mode for Timer 2
Figure 11.28 16-Bit PPG Mode Timming chart for Timer 2
Figure 11.29 16-Bit Timer 2 Block Diagram
Timer 3,
Figure 11.30 8-Bit Timer/Counter Mode for Timer 3, 4
Figure 11.31 16-Bit Timer/Counter Mode for Timer 3
Figure 11.32 8-Bit Capture Mode for Timer 3, 4
Figure 11.33 16-Bit Capture Mode for Timer 3
Table 11-12 PWM Frequency vs. Resolution at 8 MHz
Figure 11.34 10-Bit PWM Mode (Force 6-ch)
Figure 11.35 10-Bit PWM Mode (Force All-ch)
Figure 11.36 Example of PWM at 4 MHz
Figure 11.38 Example of PWM Output Waveform
Figure 11.40 Example of Phase Correction and Frequency correction of PWM
Figure 11.42 Example of Force Drive All Channel with A-ch
Figure 11.43 Example of Force Drive 6-ch Mode
Figure 11.44 Example of PWM Delay
Figure 11.45 Two 8-Bit Timer 3, 4 Block Diagram
Figure 11.46 16-Bit Timer 3 Block Diagram
Table 11-14 Timer 3, 4 Register Map
Buzzer Driver
Table 11-16 Buzzer Driver Register Map
Figure 11.49 SPI 2 Block Diagram
Table 11-17 SPI 2 Register Map
Bit A/D Converter
Figure 11.52 12-bit ADC Block Diagram
Figure 11.55 ADC Operation for Align Bit
Figure 11.56 A/D Converter Operation Flow
USI0 (UART + SPI + I2C)
Figure 11.57 USI0 UART Block Diagram
Figure 11.58 Clock Generation Block Diagram (USI0)
Figure 11.59 Synchronous Mode SCK0 Timing (USI0)
Figure 11.60 Frame Format (USI0)
Figure 11.61 Asynchronous Start Bit Sampling (USI0)
Figure 11.63 Stop Bit Sampling and Next Start Bit Sampling (USI0)
Table 11-20 CPOL0 Functionality
Figure 11.64 USI0 SPI Clock Formats when CPHA0=0
Figure 11.65 USI0 SPI Clock Formats when CPHA0=1
Figure 11.66 USI0 SPI Block Diagram
Figure 11.67 Bit Transfer on the I2C-Bus (USI0)
Figure 11.68 START and STOP Condition (USI0)
Figure 11.70 Acknowledge on the I2C-Bus (USI0)
Figure 11.71 Clock Synchronization during Arbitration Procedure (USI0)
Figure 11.73 Formats and States in the Master Transmitter Mode (USI0)
Figure 11.74 Formats and States in the Master Receiver Mode (USI0)
Figure 11.75 Formats and States in the Slave Transmitter Mode (USI0)
Figure 11.76 Formats and States in the Slave Receiver Mode (USI0)
Figure 11.77 USI0 I2C Block Diagram
Table 11-21 USI0 Register Map
USI1 (UART + SPI + I2C)
Figure 11.78 USI1 UART Block Diagram
Figure 11.79 Clock Generation Block Diagram (USI1)
Figure 11.80 Synchronous Mode SCK1 Timing (USI1)
Figure 11.81 Frame Format (USI1)
Figure 11.82 Asynchronous Start Bit Sampling (USI1)
Figure 11.84 Stop Bit Sampling and Next Start Bit Sampling (USI1)
Table 11-23 CPOL1 Functionality
Figure 11.85 USI1 SPI Clock Formats when CPHA1=0
Figure 11.86 USI1 SPI Clock Formats when CPHA1=1
Figure 11.87 USI1 SPI Block Diagram
Figure 11.88 Bit Transfer on the I2C-Bus (USI1)
Figure 11.89 START and STOP Condition (USI1)
Figure 11.91 Acknowledge on the I2C-Bus (USI1)
Figure 11.92 Clock Synchronization during Arbitration Procedure (USI1)
Figure 11.94 Formats and States in the Master Transmitter Mode (USI1)
Figure 11.95 Formats and States in the Master Receiver Mode (USI1)
Figure 11.96 Formats and States in the Slave Transmitter Mode (USI1)
Figure 11.97 Formats and States in the Slave Receiver Mode (USI1)
Figure 11.98 USI1 I2C Block Diagram
Table 11-24 USI1 Register Map
Table 11-25 Examples of USI0BD and USI1BD Settings for Commonly Used Oscillator Frequencies
LCD Driver
Figure 11.99 LCD Circuit Block Diagram
Figure 11.100 LCD Signal Waveforms (1/2Duty, 1/2Bias)
Figure 11.101 LCD Signal Waveforms (1/3Duty, 1/3Bias)
Figure 11.102 LCD Signal Waveforms (1/4Duty, 1/3Bias)
Figure 11.103 LCD Signal Waveforms (1/8Duty, 1/4Bias)
Figure 11.104 Internal Resistor Bias Connection
Figure 11.105 External Resistor Bias Connection
Figure 11.106 LCD Circuit Block Diagram
Table 11-27 LCD Frame Frequency
Power Down Operation
IDLE Mode
STOP Mode
Release Operation of STOP Mode
Table 12-2 Power Down Operation Register Map
RESET
RESET Noise Canceller
Figure 13.5 Configuration Timing when Power-on
Table 13-2 Boot Process Description
External RESETB Input
Brown Out Detector Processor
LVI Block Diagram
Register Map
On-chip Debug System
Two-Pin External Interface
Figure 14.3 Data Transfer on the Twin Bus
Figure 14.5 Start and Stop Condition
Figure 14.7 Clock Synchronization during Wait Procedure
Figure 14.8 Connection of Transmission
Flash Memory
Figure 15.1 Flash Program ROM Structure
Table 15-1Flash Memory Register Map
Figure 15.2 Flow of Protection for Invalid Erase/Write
Configure Option
APPENDIX

Abov MC96F6432Q manuals

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MC96F6432Q