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NXP Semiconductors MPC5777C manuals

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MPC5777C

Brand: NXP Semiconductors | Category: Motherboard
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Overview
  5. document organization
  6. Typographic notation
  7. References
  8. PCM memory map and register descriptions
  9. FEC Burst Optimization Master Control Register (PCM_FBOMCR)
  10. Bus Bridge Configuration Register 1 (PCM_IAHB_BE1)
  11. Bus Bridge Configuration Register 2 (PCM_IAHB_BE2)
  12. Chip-specific M_CAN information
  13. Functional Description
  14. External Signals
  15. block diagram
  16. Dual Clock Sources
  17. Memory Map and Register Description
  18. Core Release Register (M_CAN_CREL)
  19. Endian Register (M_CAN_ENDN)
  20. Fast Bit Timing and Prescaler Register (M_CAN_FBTP)
  21. Test Register (M_CAN_TEST)
  22. RAM Watchdog Register (M_CAN_RWD)
  23. CC Control Register (M_CAN_CCCR)
  24. Bit Timing and Prescaler Register (M_CAN_BTP)
  25. Timestamp Counter Configuration Register (M_CAN_TSCC)
  26. Timeout Counter Configuration Register (M_CAN_TOCC)
  27. Timeout Counter Value Register (M_CAN_TOCV)
  28. Error Counter Register (M_CAN_ECR)
  29. Protocol Status Register (M_CAN_PSR)
  30. Interrupt Register (M_CAN_IR)
  31. Interrupt Enable Register (M_CAN_IE)
  32. Interrupt Line Select Register (M_CAN_ILS)
  33. Interrupt Line Enable Register (M_CAN_ILE)
  34. Global Filter Configuration Register (M_CAN_GFC)
  35. Standard ID Filter Configuration Register (M_CAN_SIDFC)
  36. Extended ID Filter Configuration Register (M_CAN_XIDFC)
  37. Extended ID and Mask Register (M_CAN_XIDAM)
  38. New Data 1 Register (M_CAN_NDAT1)
  39. New Data 2 Register (M_CAN_NDAT2)
  40. Rx FIFO 0 Status Register (M_CAN_RXF0S)
  41. Rx FIFO 0 Acknowledge Register (M_CAN_RXF0A)
  42. Rx Buffer Configuration Register (M_CAN_RXBC)
  43. Rx FIFO 1 Status Register (M_CAN_RXF1S)
  44. Rx FIFO 1 Acknowledge Register (M_CAN_RXF1A)
  45. Rx Buffer / FIFO Element Size Configuration Register (M_CAN_RXESC)
  46. Tx Buffer Configuration Register (M_CAN_TXBC)
  47. Tx FIFO/Queue Status Register (M_CAN_TXFQS)
  48. Tx Buffer Element Size Configuration (M_CAN_TXESC)
  49. Tx Buffer Request Pending Register (M_CAN_TXBRP)
  50. Tx Buffer Add Request Register (M_CAN_TXBAR)
  51. Tx Buffer Transmission Occurred Register (M_CAN_TXBTO)
  52. Tx Buffer Transmission Interrupt Enable Register (M_CAN_TXBTIE)
  53. Tx Event FIFO Configuration Register (M_CAN_TXEFC)
  54. Tx Event FIFO Status Register (M_CAN_TXEFS)
  55. Tx Event FIFO Acknowledge Register (M_CAN_TXEFA)
  56. Rx Buffer and FIFO Element
  57. Tx Buffer Element
  58. Tx Event FIFO Element
  59. Standard Message ID Filter Element
  60. Extended Message ID Filter Element
  61. operating modes
  62. Timeout Counter
  63. Tx Handling
  64. FIFO Acknowledge Handling
  65. Interface to DMA Controller
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