NXP Semiconductors MPC5777C manuals
MPC5777C
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Overview
- document organization
- Typographic notation
- References
- PCM memory map and register descriptions
- FEC Burst Optimization Master Control Register (PCM_FBOMCR)
- Bus Bridge Configuration Register 1 (PCM_IAHB_BE1)
- Bus Bridge Configuration Register 2 (PCM_IAHB_BE2)
- Chip-specific M_CAN information
- Functional Description
- External Signals
- block diagram
- Dual Clock Sources
- Memory Map and Register Description
- Core Release Register (M_CAN_CREL)
- Endian Register (M_CAN_ENDN)
- Fast Bit Timing and Prescaler Register (M_CAN_FBTP)
- Test Register (M_CAN_TEST)
- RAM Watchdog Register (M_CAN_RWD)
- CC Control Register (M_CAN_CCCR)
- Bit Timing and Prescaler Register (M_CAN_BTP)
- Timestamp Counter Configuration Register (M_CAN_TSCC)
- Timeout Counter Configuration Register (M_CAN_TOCC)
- Timeout Counter Value Register (M_CAN_TOCV)
- Error Counter Register (M_CAN_ECR)
- Protocol Status Register (M_CAN_PSR)
- Interrupt Register (M_CAN_IR)
- Interrupt Enable Register (M_CAN_IE)
- Interrupt Line Select Register (M_CAN_ILS)
- Interrupt Line Enable Register (M_CAN_ILE)
- Global Filter Configuration Register (M_CAN_GFC)
- Standard ID Filter Configuration Register (M_CAN_SIDFC)
- Extended ID Filter Configuration Register (M_CAN_XIDFC)
- Extended ID and Mask Register (M_CAN_XIDAM)
- New Data 1 Register (M_CAN_NDAT1)
- New Data 2 Register (M_CAN_NDAT2)
- Rx FIFO 0 Status Register (M_CAN_RXF0S)
- Rx FIFO 0 Acknowledge Register (M_CAN_RXF0A)
- Rx Buffer Configuration Register (M_CAN_RXBC)
- Rx FIFO 1 Status Register (M_CAN_RXF1S)
- Rx FIFO 1 Acknowledge Register (M_CAN_RXF1A)
- Rx Buffer / FIFO Element Size Configuration Register (M_CAN_RXESC)
- Tx Buffer Configuration Register (M_CAN_TXBC)
- Tx FIFO/Queue Status Register (M_CAN_TXFQS)
- Tx Buffer Element Size Configuration (M_CAN_TXESC)
- Tx Buffer Request Pending Register (M_CAN_TXBRP)
- Tx Buffer Add Request Register (M_CAN_TXBAR)
- Tx Buffer Transmission Occurred Register (M_CAN_TXBTO)
- Tx Buffer Transmission Interrupt Enable Register (M_CAN_TXBTIE)
- Tx Event FIFO Configuration Register (M_CAN_TXEFC)
- Tx Event FIFO Status Register (M_CAN_TXEFS)
- Tx Event FIFO Acknowledge Register (M_CAN_TXEFA)
- Rx Buffer and FIFO Element
- Tx Buffer Element
- Tx Event FIFO Element
- Standard Message ID Filter Element
- Extended Message ID Filter Element
- operating modes
- Timeout Counter
- Tx Handling
- FIFO Acknowledge Handling
- Interface to DMA Controller
MPC5777C
Table of contents
- Clock calculator design
- Tree
- NXP Semiconductors
- Device Select
- Oscillator control
- FlexCAN clocking and MCAN clocking
- LFAST clocking
- PLLx
- MPC5777C Clock Calculator Guide, Rev. 1
- Limits
- Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz
- Select the Device
- Configure PER_CLK
- Observe the registers
- Copy the code
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