NEC PD17062 manuals
PD17062
Table of contents
- PWM
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- PIN FUNCTIONS
- EQUIVALENT CIRCUITS OF THE PINS
- PROGRAM MEMORY (ROM)
- FUNCTIONS OF PROGRAM MEMORY
- BRANCHING A PROGRAM
- TABLE REFERENCE
- PROGRAM COUNTER (PC)
- STACK
- ADDRESS STACK REGISTERS (ASRs)
- DATA MEMORY (RAM)
- FUNCTIONS OF DATA MEMORY
- NOTES ON USING DATA MEMORY
- GENERAL-PURPOSE REGISTER (GR)
- ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND DATA MEMORY IN INDIVIDUAL INSTRUCTIONS
- NOTES ON USING THE GENERAL-PURPOSE REGISTER
- ARITHMETIC LOGIC UNIT (ALU) BLOCK
- CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK
- NOTES ON USING THE ALU
- SYSTEM REGISTER (SYSREG)
- ADDRESS REGISTER (AR)
- BANK REGISTER (BANK)
- INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP)
- GENERAL-PURPOSE REGISTER POINTER (RP)
- REGISTER FILE (RF)
- IDCDMAEN (00H, b 1 )
- SERIAL INTERFACE MODE REGISTER (08H)
- BTM0MD (09H)
- HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)
- PLL REFERENCE MODE SELECTION REGISTER (13H)
- TIMER CARRY (17H)
- A/D CONVERTOR CONTROL (21H)
- PORT1C I/O SETTING (27H)
- INTERRUPT PERMISSION FLAG (2FH)
- IDCEN (31H)
- P1BBIOn (35H)
- P0ABIOn (37H)
- SHIFT CLOCK FREQUENCY SETTING (39H)
- DATA BUFFER (DBF)
- FUNCTIONS OF DATA BUFFER
- DATA BUFFER AND TABLE REFERENCING
- DATA BUFFER AND PERIPHERAL HARDWARE
- DATA BUFFER AND PERIPHERAL REGISTERS
- PRECAUTIONS WHEN USING DATA BUFFERS
- INTERRUPT BLOCK CONFIGURATION
- INTERRUPT FUNCTION
- INTERRUPT ACCEPTANCE
- OPERATIONS AFTER INTERRUPT ACCEPTANCE
- INTERRUPT PROCESSING ROUTINE
- INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)
- MULTIPLE INTERRUPTS
- TIMER CONFIGURATION
- TIMER FUNCTIONS
- TIMER CARRY FLIP-FLOP (TIMER CARRY FF)
- CAUTIONS IN USING THE TIMER CARRY FF
- TIMER INTERRUPT
- CAUTIONS IN USING THE TIMER INTERRUPT
- STANDBY BLOCK CONFIGURATION
- STANDBY FUNCTION
- DEVICE OPERATION MODE SPECIFIED AT THE CE PIN
- HALT FUNCTION
- CLOCK STOP FUNCTION
- OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP
- RESET BLOCK CONFIGURATION
- RESET FUNCTION
- CE RESET
- POWER-ON RESET
- RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET
- POWER FAILURE DETECTION
- CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT
- FUNCTIONS OF GENERAL-PURPOSE PORTS
- GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)
- GENERAL-PURPOSE INPUT PORT (P0D)
- GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)
- SERIAL INTERFACE MODE REGISTER
- CLOCK COUNTER
- STATUS REGISTER
- WAIT REGISTER
- PRESETTABLE SHIFT REGISTER (PSR)
- SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)
- SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)
- PWM PINS
- PLL FREQUENCY SYNTHESIZER CONFIGURATION
- OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK
- PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER
- REFERENCE FREQUENCY GENERATOR (RFG)
- PHASE COMPARATOR ( -DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK
- PLL DISABLE MODE
- SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER
- PRINCIPLE OF OPERATION
- D/A CONVERTER CONFIGURATION
- REFERENCE VOLTAGE SETTING REGISTER (ADCR)
- ADC PIN SELECT REGISTER (ADCCHn)
- EXAMPLE OF A/D CONVERSION PROGRAM
- SPECIFICATION OVERVIEW AND RESTRICTIONS
- DIRECT MEMORY ACCESS
- IDC ENABLE FLAG
- VRAM
- CHARACTER ROM
- BLANK, R, G, AND B PINS
- SPECIFYING THE DISPLAY START POSITION
- SAMPLE PROGRAMS
- HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION
- GATE CONTROL REGISTER (HSCGT)
- HSYNC COUNTER (HSC)
- OUTLINE OF INSTRUCTION SETS
- INSTRUCTIONS
- LIST OF INSTRUCTION SETS
- BUILT-IN MACRO INSTRUCTIONS
- RESERVED SYMBOLS FOR ASSEMBLER
- PORT REGISTER
- REGISTER FILES
- PERIPHERAL HARDWARE REGISTER
- ELECTRICAL CHARACTERISTICS
- PACKAGE DRAWINGS
- RECOMMENDED SOLDERING CONDITIONS
- APPENDIX DEVELOPMENT TOOLS
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