238 APPENDIX B: PATH BUILDER S330/S310 MODULE AND APPLICATION OVERVIEWSetting up a VirtualCircuitTo configure a circuit in the PathBuilder S330/S310, you must set up a virtualcircuit between any two ports through the CTX. See “Configuring Virtual Circuits”in Chapter 4, for details about setting up virtual circuits.VPI and VCI RangesAs explained earlier in this chapter, address translation is performed in the CTX.For VP connections, the full 8 bits of the VPI is looked up, so up to 256 VPconnections are supported per port. For VC connections, only two LSB VPI bits and8 LSB VCI bits are considered. So, for VC connections, VPs 0 through 3 and VCs 1through 255 are the only ones supported.Early and Partial PacketDiscardEarly packet discard (EPD) and partial packet discard (PPD) functions are providedon the CTX for every connection. EPD and PPD are enabled per VC for those VCscarrying AAL5 traffic.For EPD, every output queue contains two thresholds that you can set: congestionON and congestion OFF. You set these thresholds by percentage. See “SettingCongestion Thresholds” in Chapter 4, for details about setting congestionthresholds. Partial packet discard works when the queue is actually full and a cell isdropped for a particular connection. When this happens, the rest of the cells forthat connection are discarded until the end of packet is reached.T1/E1 UNI with IMAInterfaceThe four T1/E1 UNI with IMA interfaces allow you to connect legacy, voice, video,and data traffic to your branch offices, using either single T1s/E1s or nxT1/nxE1IMA bundles. The IMA bundles connect up to four lines from a single office site(eight lines if you have installed the optional four-port IMA expansion module).The PathBuilder S310 switch has only a single T1/E1 interface.On the T1/E1 receive side, the data flow is as follows:n A line interface unit recovers the digital data and performs the T1/E1 framingon it with DSX and CSU capability. The integral CSU eliminates the need for anexternal CSU.n The data flows through a framer to get the ATM cells.n The output of the framer interfaces to the IMA circuitry that stores the datainto memory and synchronizes the cells back. All four T1s/E1s go into the IMAbuffers where they can be treated as one group or as four separate groups(four individual T1s/E1s).n After the cells are synchronized, the IMA circuitry tags them with a groupnumber and passes them to the CTX. At the CTX interface, the cells will looklike they are coming from different groups.On the T1/E1 transmit side, the data flow is as follows:n Cells received from the CTX toward the T1/E1 groups are stored in thecorresponding buffers, as described under “CTX Output Queues and MemoryPartition” earlier in this chapter. Group 1 consists of 4 buffers; the other threegroups have two buffers each.n The cells are picked up from the queues in order of priority, under the shapercontrol, and delivered to the IMA logic.