Chapter 12. Diagnostics218 PACSystems* RX7i & RX3i TCP/IP Ethernet Communications User Manual GFK-2224QChannel Status BitsThe Channel Status bits provide runtime status information for each communication channel. Each channelhas two status bits; the meaning of the channel status bits depends upon the type of communicationperformed on that channel.Modbus TCP Client ChannelsEach Modbus channel has a dedicated status bit:Bits 17, 19, 21 ... 79, Connection Open Bit (Rack-based and RX7i Embedded)Bits 17, 19, 21 ... 47, Connection Open Bit (RX3i Embedded)This bit is 1 when a TCP connection exists for the associated channel. The bit is 0 when the connection does notexist or is unused (either never created or has disconnected). The bit is also set to zero when the controller goesto STOP, because all connections are automatically closed upon STOP transition.Bits 18, 20, 22 ...46, 48–80, Reserved (All models)When a Channel is used as a Modbus TCP Channel, these bits are not used.SRTP Client ChannelsEach SRTP channel has two status bits: a Data Transfer bit and a Channel Error bit.Bits 17, 19, 21 ... 79, Data Transfer Bit (Rack-based and RX7i Embedded)Bits 17, 19, 21 ... 47, Data Transfer Bit (RX3i Embedded)Typically, a channel is used to perform repetitive readsor writes. The Data Transfer bit pulses (0 1 0) each time there is a successful read or write. This can be anindicator to the ladder program to move the most recent data to another location.This bit is not closely synchronized in time with the transfer. It indicates only that a transfer has occurred duringthe preceding read or write period. A rising edge on the bit indicating that a transfer has completed does notguarantee that the next transfer has not begun or completed.After an Establish Channel command, the COMM_REQ status word (CSW) is always updated before the DataTransfer bit is set to 1. The Data Transfer bit for a channel is not meaningful until the Ethernet Interface updatesthe CSW. Do not use data received from a server until the CSW confirming the Read command for that channelis 1 and the Data Transfer bit goes to 1.Bits 18, 20, 22 ... 80, Channel Error Bit (Rack-based and RX7i Embedded)Bits 18, 20, 22 ... 48, Channel Error Bit (RX3i Embedded)This bit (normally 0) is the primary indicator for an error on a channel. It indicates any channel error, fatal ornon-fatal. It does not necessarily indicate that the channel is idle.A Channel Error bit is not meaningful until the Ethernet Interface has updated the COMM_REQ status wordconfirming the Read or Write command for that channel. For an Establish Channel command, the COMM_REQstatus word is updated before the Channel Error bit is set to 1.▪ A Channel Error bit is set to 1 when an error is detected on the channel. It is set to 0 when the channelis initially established and if the channel resumes normal operation after a transient error conditionsubsides. The Channel Error bit is also set to 0 when the channel is aborted by an Abort Channelcommand or when the CPU transitions from RUN to STOP. In the case of an Establish Channelcommand, the COMM_REQ status word is always updated before the Channel Error bit is set to 1.▪ If this bit indicates an error, initiate the Abort command and then reinitiate the Read or Writecommand. If the error persists, initiate the Retrieve Detailed Channel Status command to find out if thechannel is idle, and possibly why it is idle. The status code may change between the time the ChannelError bit indicates an error and the time the Retrieve Detailed Channel Status command retrieves thecode.
