Kenwood NXR-800 Service Manual

Also see for NEXEDGE NXR-800: Brochure Instruction manual Instruction manual Instruction manual Instruction manual

Contents

NXR-800164-5. Squelch circuitThe desired noise of the noise component output from IFsystem IC_IC12 (pin18) is extracted by the BPF. After pass-ing through Q40, it is DC-detected as the squelch voltage byD17, D18 and input to ADC_IC30 (pin11).The MPU mounted in the control unit (X53-413) comparesit with a predetermined reference voltage and turns the Au-dio signal on and off. The strength of the receiver signal in-put from CN5 is output as the RSSI voltage from IF systemIC_IC12 (pin21), and is input to_IC30 (ADC) pin12 via IC29A/2.4-6. Receiver DDS circuitThe 19.2MHz Internal reference clock produced by trans-mitter unit (X56-312 A/3) is distributed to CN45 of the re-ceiver unit (X55-310). It passes through Q39, Q30, and IC8,and is input to IC7 (DDS-IC) pin6 as the Master clock. Ap-proximately 6MHz signal is generated as the 1st-PLL Refer-ence clock.IC7 has a resolution of 32 bits for realizing the frequencystep minters than the 1st-PLL comparison frequency. Thegenerated Reference clock is output via Q12, CF1, and Q5.CF1 is a Ceramic Filter. It is the BPF for removing unneces-sary spurious noise included in the generated Referenceclock.D15SWD16SWCF2CF3D19SWD20SWDETCF5CF7QUAD108641517 IC20(A/2)Q40IC29 (A/2)D17,18IC3011 181218212414 8 10DIV2nd local49.5MHz2nd local49.5MHz6CF4CF6145DR3DR5NRAnalog WideAnalog NarrowNXDN NarrowNXDN Very-NarrowIC12IC13IC14CN421222CN43LPF LPF LPF LPFBPF+5VQ5+5V +5VQ12+5VQ30+5VQ39CF1IC7DDS14 6+5VIC81 5DIV CN45Fig. 19 Demodulator circuitsFig. 20 Receiver DDS circuitCIRCUIT DESCRIPTION