TK-2107G112-5. SquelchPart of the AF signal from the IC enters the FM IC again,and the noise component is amplified and rectified by a filterand an amplifier to produce a DC voltage corresponding tothe noise level.The DC signal from the FM IC goes to the analog port ofthe microprocessor (IC403). IC403 determines whether tooutput sounds from the speaker by checking whether theinput voltage is higher or lower than the preset value.To output sounds from the speaker, IC403 sends a highsignal to the MUTE and AFCO Iines and turns IC302 onthrough Q302, Q304, Q305, Q306 and Q307. (See Fig. 3)2-5. 噪音抑制电路从 I C200 输出的音频信号的一部分重新进入 I C200,通过滤波器和放大器将噪音放大和整流并生成一个对应于噪音电平的直流电压。直流信号进入微处理器的模拟端口 ( I C403)。IC403 通过检测输入电压是否高于或低于预设值来决定是否通过扬声器输出声音。要通过扬声器输出声音,I C403 向静音和自动频率控制振荡器连线发送一个高电平信号并开启 I C302 通过 Q302, Q304,Q305,Q306 和 Q307。( 参见图 3)2-6. Receive signaling• QT/DQT300Hz and higher audio frequencies of the output signalfrom IF IC are cut by a low-pass filter (IC301). The resultingsignal enters the microprocessor (IC403). IC403 determineswhether the QT or DQT matches the preset value, and con-trols the MUTE and AFCO and the speaker output soundsaccording to the squelch results.3. PLL Frequency SynthesizerThe PLL circuit generates the first local oscillator signalfor reception and the RF signal for transmission.3-1. PLLThe frequency step of the PLL circuit is 5 or 6.25kHz. A12.8MHz reference oscillator signal is divided at IC1 by afixed counter to produce the 5 or 6.25kHz reference fre-quency. The voltage controlled oscillator (VCO) output signalis buffer amplified by Q6, then divided in IC1 by a dual-mod-ule programmable counter. The divided signal is comparedin phase with the 5 or 6.25kHz reference signal in the phasecomparator in IC1. The output signal from the phase com-parator is filtrered through a low-pass filter and passed tothe VCO to control the oscillator frequency. (See Fig. 4)2-6. 接收信令• QT/DQT来自于中频芯片输出信号的 300H z 和更高的音频被低频滤波器 ( Q301) 截断。所得到的信号输入微处理器 ( I C403)。I C403 确定 Q T 或 D Q T 是否匹配预设置,并且根据噪声抑制电路的结果控制 MUTE 和 AFCO 以及扬声器输出声音。3. 锁相环频率合成器锁相环电路生成用于接收的第一本振信号和用于发送的射频载波信号。3-1. 锁相环电路锁相环电路的步进频率为 5 或 6.25k H z。12.8M H z 的参考振荡器信号通过一个混合计数器在 I C1 中被分频并生成 5 或6.25k H z 的参考频率。压控振荡器 ( V C O ) 输出的信号通过 Q6缓冲放大器,然后在 I C1 中被可编程脉冲吞除计数器分频。被分频的信号在带有 5 或 6.25k H z 参考信号的相位比较器的IC1 中被比较。从相位比较器输出的信号进入一个低通滤波器后,并通过压控振荡器来控制振荡频率。( 参见图 4)Fig. 3 AF amplifier and Squelch / 图 3 音频放大器和噪音抑制电路CIRCUIT DESCRIPTION / 电路说明IC200: FM IF ICIF AMPDETDETHPF AMPBUSYMUTEAFCOTI656762IC301LPFQT/DQTQ303W/N SWIC403MCUAF AMPIC300LPF HPF Q302SWIC302AF PA AMP SPQ304~Q306SWQ307SW