Kenwood TK-885 Service Manual

Also see for TK-885: Instruction manual Service manual

Contents

14TK-885 Squelch CircuitThe detection output from the FM IF IC (IC11) is ampli-fied by IC2 and the signal (DEO) is sent to the control unit.The signal passes through a high-pass filter and a noise am-plifier (Q503) in the control unit to detect noise. A voltage isapplied to the CPU (IC511). The CPU controls squelch ac-cording to the voltage (ASQ) level. The signal from the RSSIpin of IC11 is monitored. The electric field strength of thereceive signal can be known before the ASQ voltage is inputto the CPU, and the scan stop speed is improved.IC2AMPIC503AMPQ503NOISE AMP D509IC11 IC511DEORSSIHPF DETCPUIFSYSTEMCONTROL UNITFig. 4 Squelch circuitFig. 5 Transmitter systemCIRCUIT DESCRIPTIONTransmitter System OutlineThe transmitter circuit produces and amplifies the de-sired frequency directly. It FM-modulates the carrier signalby means of a varicap diode. VCO/PLL CircuitThe TK-885 has a VCO for the transmitter and a VCO forthe receiver in a sub-unit (A1). They are housed in a solidshielded case and connected to the TX-RX unit throughCN101. One of the VCOs is selected with an ST signal. Afiltered low-noise power supply is used for the VCOs andvaricap diodes.The VCO for the transmitter is described below. It is de-signed so that Q103 turns on with a prescribed frequencywhen a reverse bias is applied to D102 and D104 by usingthe control voltage (CV) through CN101. The control voltageis changed by turning the trimmer capacitor (TC109). Theoutput from Q103 is applied to the buffer amplifier (Q106) togenerate a VCO output signal. This signal is used as a driveinput signal or a local signal of the first mixer.Since a signal output from Q106 is input to the PLL IC, itpasses through CN101 and buffer amplifier (Q300) and goesto the PLL IC (IC300). The modulation signal from CN101 isapplied to D105 and passes through C113 to modulate thecarrier.The PLL IC uses a fractional N type synthesizer to im-prove the C/N ratio and lock-up speed. The VCO output sig-nal input to the pin 5 of the PLL IC is divided to produce acomparison frequency according to a channel step. This sig-nal is compared with the reference frequency which is out-put from the VCXO (X1). VCXO provides 16.8MHz, 2.5ppm(–30 to +60°C) and guarantees stable performance whenthe temperature changes. The output signal from the phasecomparator passes through a charge pump and an externalactive LPF (Q301, Q302) in the PLL IC to generate a DC VCOcontrol voltage CV. Serial data (DT, CK, EP) are output fromthe CPU (IC511) and shift register (IC8) in the control unit tocontrol the PLL IC. The PLL lock status is always monitoredby the CPU. Unlock CircuitDuring reception, the T/R signal goes high, the KEY signalgoes low, and Q10 turns on. Q11 turns on and a voltage isapplied to the collector (8R). During transmission, the T/Rsignal goes low, the KEY signal goes high and Q13 turns on.Q12 turns on and a voltage is applied to 8T.The CPU in the control unit monitors the PLL (IC300) LDsignal directly. The CPU detects this signal and makes theKEY signal low. When the KEY signal goes low, no voltageis applied to 8T, and no signal is transmitted.IC508SHIFTREG.IC511CPUQ10SWQ11SWIC300PLLQ13SWQ12SWLDCONTROL UNITT/R8C8R 8TKEYPLL lock: LD "H"Fig. 6 Unlock circuitIC504 IC3 Q103IC711MICAF AMPTA75S01FMIC KEYINPUTAF AMP,IDC, LPFTC35453FIC511CPU30620M8-394GPSUM AMPTA75W558FUX1VCXO16.8MHzVCO2SK508NV(K53)IC300PLLSA7025DKQ106RF AMP2SC4226(R24)Q300BUFFER2SC4215(Y)Q202RF AMP2SC4093(R27)Q204RF AMP2SC3357Q205ANTRF AMP2SC2954IC400POWER AMPM57729HQ7BUFFER2SC5110(O)