NXP Semiconductors Freescale MCIMX53SMD Hardware User's Manual

Distributor of NXP Semiconductors: Excellent Integrated System LimitedDatasheet of MCIMX53SMD - TABLET SABRE PLATFORM MCIMX53Contact us: sales@integrated-circuit.com Website: www.integrated-circuit.com34 MCIMX53SMD Board Hardware User’s Guide, Rev. 0 Freescale SemiconductorDCIN_SEL (B3) pin and the P-Channel MOSFET turns ON. Otherwise, DCIN_SEL remains high and power isblocked from the rest of the MCIMX53SMD board.The TP (L5) pin of the PMIC must be connected to ground. When designing with a 0.5 mm pitch uBGA package,there is limited space for vias and traces under the BGA. To assist with layout, Freescale has confirmed that allpins labeled ‘NO CONNECT’ on the PMIC are no manner bonded out to the silicon. Therefore, for routingpurposes, it is possible to route the trace from an interior pin through one or more ‘NO CONNECT’ pins, or toplace a via directly under a ‘NO CONNECT’ pin without requiring a via-in-pad technique. If the CAD LayoutEngineer decides to place a via under a ‘NO CONNECT’ pin, the via should not be tented as trapped gasesduring the assembly process, as this may cause the solder ball from the ‘NO CONNECT’ pin to blow out intoother pins and cause internal shorts under the BGA.The I2C communications channel between the processor and the PMIC is channel 1. This channel is onlyshared with the accelerometer. This channel operates at TTL logic level of 1.8V. The NRESET (F10) pin of thePMIC is directly connected to the Active Low POR_B (C19) pin of the i.MX processor. The PMIC will hold theprocessor in the RESET state until all the power rails are fully powered. The NIRQ (E10) pin of the PMIC isconnected to the GPIO_ 16 (C6) pin of the processor. This pin is not a dedicated pin for an interrupt request,but can be programmed in the software to inform the processor that the PMIC has information to be sent tothe processor.The PMIC has several different options for Pull-Up levels on each of its output pins. In some cases, VDDOUT isone option, along with power supplied to both the VDD_IO1 (L4) and VDD_IO2 (K4) pins as Pull-Up source. Theexact source of Pull-Up power is determined by the registry settings of the PMIC and can be pre-programmedat the factory as the designer wishes. Some Pull-Up registry settings apply to groups of pins, so care must betaken in selecting the power source for a particular group of pins. See the Dialog PMIC data sheet for moredetailed information on registry settings. For the MCIMX53SMD board, VLDO3 (3.3V) is connected to VDD_IO1primarily to ensure that the 3V3_EN signal sent to the external regulator is sufficient to turn ON the regulator.Similarly, VLDO8 (1.8V) is connected to VDD_IO2 to provide proper I2C TTL logic levels.5.3. i.MX53 Applications ProcessorThe i.MX53 Applications Processor is physically located in the central portion of the MCIMX53SMD board. Themost critical components for placement after the processor are the DDR3 SDRAM ICs. The remainingcomponents and connectors are arranged around the periphery of the board in locations that minimize tracerouting. The i.MX53 processor is a highly integrated system-on-chips with many modules controlled by themain ARM Cortex-A8 core. Most modules have Logic Voltage inputs that allow the designer to modify logiclevels to suit the needs of connected ICs. A more detailed explanation of these Logic Voltage Inputs ispresented in the Peripheral Module Logic Voltage Levels subsection. The information for voltage levels andother chip specific details come from the i.MX53 data sheet, which is updated time to time.The i.MX53 processor initializes out of reset according to its preprogrammed ROM code. After initial wakeup,it attempts to read the logic levels on 26 different pins. Depending on which pins are high/low, the processorselects one of the allowed boot options to begin the boot process. This is further explained in the Boot ModeOperations and Selections subsection.The clock signals required by the i.MX53 processor and the rest of the MCIMX53SMD board are furtherexplained in the Clock Signals subsection. The i.MX53 processor has the ability to supply a limited amount offiltered power for internal purposes using an internal voltage regulator. The operation of this regulator isexplained further in the i.MX53 Internal Regulator subsection. The Processor also has an internal Watch DogTimer (WDOG) circuit that can be used to reset the Processor in the event it stops functioning correctly. Thesupported circuitry is explained further in the Watch Dog Time subsection.