NXP Semiconductors Freescale MCIMX6Q-SL User Manual

MCIMX6Q-SL: Development platform for i.MX 6QuadBuilt to Freescale® SABRE Lite designDoc ID: MCIMX6QSLUMRev. 0.9, 11/12/2012Embest and element14 are trademarks of Premier Farnell plc 10© 2012 Premier Farnell plc. All Rights ReservedFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.3 Hardware Description3.1 ProcessorThe i.MX 6Dual/6Quad processors represents Freescale Semiconductor’s latest achievement in integratedmultimedia applications processors, which are part of a growing family of multimedia-focused products thatoffer high performance processing and are optimized for lowest power consumption.The processor features Freescale’s advanced implementation of the quad ARM™ Cortex-A9 core, whichoperates at speeds up to 1GHz. They include 2D and 3D graphics processors, 3D 1080p video processing, andintegrated power management. Each processor provides a 64-bit DDR3/LVDDR3-1066 memory interface and anumber of other interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, hard drive, displays,and camera sensors.3.1.1 Core FeaturesThe i.MX 6Dual/6Quad processors are based on the ARM Cortex A9 MPCore™ platform with the followingfeatures:• ARM Cortex A9 MPCore™ 4xCPU Processor (with TrustZone)• The core configuration is symmetric, where each core includes:o 32 KByte L1 Instruction Cacheo 32 KByte L1 Data Cacheo Private Timer and Watchdogo Cortex-A9 NEON MPE (Media Processing Engine) Co-processor• The ARM Cortex A9 MPCore™ complex includes:o General Interrupt Controller (GIC) with 128 interrupt supporto Global Timero Snoop Control Unit (SCU)o 1 MB unified I/D L2 cache, shared by two/four coreso Two Master AXI (64-bit) bus interfaces output of L2 cacheo Target frequency of the core (including Neon and L1 cache) is:o 1 GHz overdrive over the specified temperature rango 900 MHz non-overdrive over the specified temperature rangeo NEON MPE coprocessoro SIMD Media Processing Architectureo NEON register file with 32x64bit general-purpose registerso NEON Integer execute pipeline (ALU, Shift, MAC)o NEON dual, single-precision floating point execute pipeline (FADD, FMUL)o NEON load/store and permute pipeline• The memory system consists of the following components:o Level 1 Cache--32 KB Instruction, 32 KB Data cache per coreo Level 2 Cache--Unified instruction and data (1 MByte)o On-Chip Memory:o Boot ROM, including HAB (96 KB)o Internal multimedia / shared,fast access RAM (OCRAM, 256 KB)o Secure/non-secure RAM (16 KB)