NXP Semiconductors Freescale MCIMX6Q-SL User Manual

MCIMX6Q-SL: Development platform for i.MX 6QuadBuilt to Freescale® SABRE Lite designDoc ID: MCIMX6QSLUMRev. 0.9, 11/12/2012Embest and element14 are trademarks of Premier Farnell plc 12© 2012 Premier Farnell plc. All Rights ReservedFreescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to fourdata lanes. Each i.MX 6Dual/6Quad processor has four lanes.• Expansion cards:o Four MMC/SD/SDIO card ports all supporting:o 1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104 mode (104MB/s max)o 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR andDDR modes (104 MB/s max)• USBo High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHYo Three USB 2.0 (480 Mbps) hostso One HS host with integrated High Speed PHYo Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY• Expansion PCI Express port (PCIe) v2.0 one laneo PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpointoperations. Uses x1 PHY configuration.• Miscellaneous IPs and interfaces:o Three I2S/SSI/AC97,up to 1.4 Mbps eacho Enhanced Serial Audio Interface ESAI), up to 1.4 Mbps per channelo Five UARTs, up to 4.0 Mbps eacho Providing RS232 interfaceo Supporting 9-bit RS485 multidrop modeo One of the five UARTs (UART1) supports 8-wir while others four supports 4-wire. This is due tothe SoC IOMUX limitation, since all UART IPs are identical.o Five eCSPI (Enhanced CSI), up to 52 Mbps eacho Three I2C, supporting 400 kbpso Gigabit Ethernet Controller(IEEE1588 compliant), 10/100/1000 Mbpso Four Pulse Width Modulators (PWM)o System JTAG Controller (SJC)o GPIO with interrupt capabilitieso 8x8 Key Pad Port (KPP)o Sony Philips Digital Interface (SPDIF), Rx and Txo Two Controller Area Network (FlexCAN), 1 Mbps eacho Two Watchdog timers (WDOG)o Audio MUX (AUDMUX)3.1.4 Advanced Power Management unitThe i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers:• Provide PMU, including DCDC and LDO supplies, for on-chip resources• Use Temperature Sensor for monitoring the die temperature• Support DVFS techniques for low power modes• Use SW State Retention and Power Gating for ARM and MPE• Support various levels of system power modes• Use flexible clock gating control scheme