Chapter 4 Signal ConnectionsPCI-6023E/6024E/6025E User Manual4-38 ©National Instruments CorporationA counter on your board internally generates the STARTSCAN signalunless you select some external source. This counter is started by theTRIG1 signal and is stopped either by software or by the sample counter.Scans generated by either an internal or external STARTSCAN signal areinhibited unless they occur within a DAQ sequence. Scans occurring withina DAQ sequence may be gated by either the hardware (AIGATE) signal orsoftware command register gate.CONVERT* SignalAny PFI pin can externally input the CONVERT* signal, which isavailable as an output on the PFI2/CONVERT* pin.Refer to Figures 4-17 and 4-18 for the relationship of CONVERT* to theDAQ sequence.As an input, the CONVERT* signal is configured in the edge-detectionmode. You can select any PFI pin as the source for CONVERT* andconfigure the polarity selection for either rising or falling edge. Theselected edge of the CONVERT* signal initiates an A/D conversion.The ADC switches to hold mode within 60 ns of the selected edge. Thishold-mode delay time is a function of temperature and does not vary fromone conversion to the next. CONVERT* pulses should be separated by atleast 5 μs (200 kHz sample rate)As an output, the CONVERT* signal reflects the actual convert pulse thatis connected to the ADC. This is true even if the conversions are beingexternally generated by another PFI. The output is an active low pulse witha pulse width of 50 to 150 ns. This output is set to tri-state at startup.Figures 4-27 and 4-28 show the input and output timing requirements forthe CONVERT* signal.Figure 4-27. CONVERT* Input Signal TimingRising-edgepolarityFalling-edgepolarityt wt w = 10 ns minimum
