National Instruments DAQ PCI-6023E User Manual

Also see for DAQ PCI-6023E: Programmer's manual

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National Instruments DAQ PCI-6023E User Manual Manual pdf 71 page image

Chapter 4 Signal ConnectionsPCI-6023E/6024E/6025E User Manual4-42 ©National Instruments CorporationFigures 4-32 and 4-33 show the input and output timing requirements forthe UPDATE* signal.Figure 4-32. UPDATE* Input Signal TimingFigure 4-33. UPDATE* Output Signal TimingThe DACs are updated within 100 ns of the leading edge. Separate theUPDATE* pulses with enough time that new data can be written to theDAC latches.The board UI counter normally generates the UPDATE* signal unless youselect some external source. The UI counter is started by the WFTRIGsignal and can be stopped by software or the internal Buffer Counter.D/A conversions generated by either an internal or external UPDATE*signal do not occur when gated by the software command register gate.UISOURCE SignalAny PFI pin can externally input the UISOURCE signal, which is notavailable as an output on the I/O connector. The UI counter uses theUISOURCE signal as a clock to time the generation of the UPDATE*signal. You must configure the PFI pin you select as the source for theUISOURCE signal in the level-detection mode. You can configure thepolarity selection for the PFI pin for either active high or active low.Figure 4-34 shows the timing requirements for the UISOURCE signal.Rising-edgepolarityFalling-edgepolarityt wt w = 10 ns minimumt wt w = 300-350 ns