2-2 | ni.comChapter 2 Analog InputAnalog Input Timing SignalsThe cDAQ chassis features the following analog input timing signals:• AI Sample Clock Signal*• AI Sample Clock Timebase Signal• AI Start Trigger Signal*• AI Reference Trigger Signal*• AI Pause Trigger Signal*Signals with an * support digital filtering. Refer to the PFI Filters section of Chapter 4, DigitalInput/Output and PFI, for more information.Refer to the AI Convert Clock Signal Behav ior For Analog Input Modules section for AI ConvertClock signals and the cDAQ chassis.AI Sample Clock SignalA sample consists of one reading from each channel in the AI task. Sample Clock signals thestart of a sample of all analog input channels in the task. Sample Clock can be generated fromexternal or internal sources as shown in Figure 2-1.Figure 2-1. AI Sample Clock Timing OptionsRouting the Sample Clock to an Output TerminalYou can route Sample Clock to any output PFI terminal. Sample Clock is an active high pulseby default.AI Sample Clock Timebase SignalThe AI Sample Clock Timebase signal is divided down to provide a source for Sample Clock.AI Sample Clock Timebase can be generated from external or internal sources. AI Sample ClockTimebase is not available as an output from the chassis.ProgrammableClockDividerAI Sample ClockTimebasePFIAnalog Comparison EventCtr n Internal Output AI Sample ClockSigma-Delta Module Internal OutputAnalog ComparisonEvent20 MHz Timebase80 MHz TimebasePFI100 kHz Timebase
