© National Instruments | 5-7NI cDAQ-9181/9184/9188/9191 User ManualThe counter counts the number of edges on the Source input while the Gate input remains active.On each sample clock edge, the counter stores the count in the FIFO of the last pulse width tocomplete. The STC3 transfers the sampled values to host memory using a high-speed datastream.Figure 5-7 shows an example of a sample clocked buffered pulse-width measurement.Figure 5-7. Sample Clocked Buffered Pulse-Width MeasurementNote If a pulse does not occur between sample clocks, an overrun error occurs.For information about connecting counter signals, refer to the Default Counter/Timer Routingsection.Pulse MeasurementIn pulse measurements, the counter measures the high and low time of a pulse on its Gate inputsignal after the counter is armed. A pulse is defined in terms of its high and low time, high andlow ticks or frequency and duty cycle. This is similar to the pulse-width measurement, exceptthat the inactive pulse is measured as well.You can route an internal or external periodic clock signal (with a known period) to the Sourceinput of the counter. The counter counts the number of rising (or falling) edges occurring on theSource input between two edges of the Gate signal.You can calculate the high and low time of the Gate input by multiplying the period of the Sourcesignal by the number of edges returned by the counter.Refer to the following sections for more information about cDAQ chassis pulse measurementoptions:• Single Pulse Measurement• Implicit Buffered Pulse Measurement• Sample Clocked Buffered Pulse MeasurementPulseSourceSample Clock2 34 2432 24Buffer
