Nuvoton CODEC 8812 series User Manual

Contents

Nuvoton CODEC 8812 series User Manual Manual pdf 32 page image

CODEC Motherboard Manual Version 1.3 Page 32 of 66 April 12, 2016CODEC Motherboard13.11 CLKM Master ClockSelecting this control bit will cause the NAU8822 device to use the PLL output as the input to itsMaster Clock (IMCLK) Prescaler. If this is not selected, the IMCLK Prescaler will use the signalon the external MCLK pin as its input.13.12 BCLKSELThis has an effect only if the NAU8822 device is the audio bus master. When the device is theaudio bus master, the internal IMCLK rate will be divided by the factor set in this panel, and thiswill become the rate of the FS signal on the FS output pin.13.13 SMPLR Sample RateThis control value does NOT change the sampling rate in any way. The SMPLR value existsbecause the digital signal processing algorithms have no information to know the actual physicalsample rate. This is determined by the external MCLK frequency. The only function of theSMPLR value is to scale the ADC high pass filter coefficients to be compensated for the actualsample rate of the system. If SMPLR is set correctly, then the high pass filter cutoff frequency willbe the desired value as listed in the NAU8822 Design Guide. The Equalizer cutoff frequencieshave no such compensation. The nominal Equalizer cutoff frequencies in the design guide arefor a 48kHz sample rate. For example, if the actual sample rate is 24kHz, then the Equalizercutoff frequencies will be one half of the values listed for 48kHz in the Design Guide.13.14 Companding ControlCompanding implements a non-linear compression/decompression of the audio signal asexplained in the NAU8822 device Design Guide. Most applications for the NAU8822 will not usethis feature.13.15 PASSTHRUWhen enabled, the pass-through mode causes data from the left and right ADC outputs to flowdirectly into the digital signal processing chain for the DAC output section. In this mode, data onthe DACIN pin are ignored and replaced with data from the corresponding ADCs. ADC datacontinues to be output on the ADCOUT pin.13.16 Audio Interface ControlThese controls affect how audio data are formatted and input or output on the serial digital audiobus and are explained in the device Design Guide. The "MONO" control does not affectformatting. This feature may be useful when only the left ADC is being used, and it is importantto guarantee that the right channel information is exactly zero.13.17 Jack Detect Bus SwitchingThese controls affect various options related to the jack detection feature as detailed in the deviceDesign Guide. The idea of jack detection is that a logic level change can be sensed on one of theGPIO pins, and this change will then enable/disable specified outputs and power control blocks.