Nuvoton CODEC 8812 series User Manual

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Nuvoton CODEC 8812 series User Manual Manual pdf 47 page image

CODEC Motherboard Manual Version 1.3 Page 47 of 66 April 12, 2016CODEC Motherboard23 Digital Audio Using the NAU8822The NAU8822 supports digital audio input and output using I2S or PCM (DSP Mode) serial datacommunications. These various paths may be used directly, or as a convenience, themotherboard provides resources to convert these formats into commonly used external formatssuch as S/PDIF and USB audio. The connectors supporting these digital audio options are listedand discussed in this section.23.1 NAU8822 Master Clock RequirementThe NAU8822 requires a high frequency master clock supplied via its MCLK pin to operate eitherthe ADC or DAC blocks inside the NAU8822. For the best audio quality, the master clock shouldbe phase locked in an integer ratio relationship with the sample clock (FS signal) of the externalsource. Further, the internal IMCLK signal clock rate to the ADC and DAC should be exactly 256times the FS sample rate. This is explained in the Design Guide for the NAU8822.23.2 Master Clock SelectionMany options are available for supplying a suitable MCLK under control of the W681308microcontroller and using the extensive MCLK management resources provided by the NAU8822.The NAU8822 also includes a fractional-N PLL (phase locked loop) that can create a suitableinternal MCLK signal using a wide range of available signals on its MCLK pin.When using S/PDIF as an audio source, the S/PDIF transceiver provides a suitable MCLK.When using USB, the W681308 provides the 12.000MHz USB clock as the MCLK signal.An external MCLK clock may be supplied directly to the device on the daughter card via TP33.To select this option, the J47 jumper selector must be moved from the default Pin 2-3 position tothe Pin 1-2 position. MCLK may also be supplied to J8, however, this SMB style connector is notpopulated on the motherboard.23.3 Frame Sync (Sample Rate Clock)The FS signal is synonymous with the sample rate of the digital audio data bus. This signal doesNOT in any way determine the ADC and DAC sample rate. For best audio quality, the masterclock inside the NAU8822 should be set up so that the ADC and DAC are running phase lockedat exactly the same sample rate as the FS signal. The FS signal is provided by the audio busmaster. The W681308 microcontroller determines which device is the bus master and sets upthe NAU8822 clock subsystem accordingly.23.4 Bit Clock (BLCK)The bit clock is a medium speed clock that initiates transfer of each audio bit in the I2S or PCMaudio data stream. This clock is synchronous with the Frame Sync and provided by the samebus master that supplies the Frame Sync signal. The only requirement for the bit clock is to havea sufficient number of clock-edge transitions to transfer all of the audio data bits in the audiosample before the next Frame Sync transition occurs.