Quatech MPAP-100 User Manual

Also see for MPAP-100: Specifications User manual

Contents

Quatech MPAP-100 User Manual Manual pdf 35 page image

9.5 SCC Incompatibility WarningsDue to the SCC implementation used by the MPAP-100, there are two minorincompatibilities that the software programmer must avoid.9.5.1 Register Pointer BitsIn a Zilog 85230, the control port register pointer bits can be set in either channel. Withthe implementation on the MPAP-100, however, both parts of an SCC control port access mustuse the same I/O address.IMPORTANTThe programmer must be certain not to mix channel usage duringthe two-part access of SCC control ports. It would be highlyirregular for code to be written in such fashion, so this restriction isnot expected to be burdensome.The following sequences will work:Write Control Port A (set pointer bits for desired register)Read or Write Control Port A (read or write desired channel A register)Write Control Port B (set pointer bits for desired register)Read or Write Control Port B (read or write desired channel B register)The following sequences will NOT work:Write Control Port A (set pointer bits for desired register)Read or Write Control Port B (read or write desired channel B register)Write Control Port B (set pointer bits for desired register)Read or Write Control Port A (read or write desired channel A register)9.5.2 Software Interrupt AcknowledgeThe 85230's software interrupt acknowledge mechanism is not supported. Bit 5 of WriteRegister 9 (Software INTACK Enable) is forced to 0. Software must employ the "InterruptWithout Acknowledge" interrupt method using Read Registers 2 and 3 to process interrupts.