Quatech MPAP-100 User Manual

Also see for MPAP-100: Specifications User manual

Contents

Quatech MPAP-100 User Manual Manual pdf 41 page image

10.4.2 Resetting the FIFOsThe FIFOs are automatically disabled and reset at powerup or when the MPAP-100 isinserted into a PCMCIA socket. The transmit and receive FIFOs can also be independently resetby setting and clearing the appropriate bits in the FIFO Control Register. Resetting a FIFO setsthe appropriate FIFO empty status bit and resets the FIFO's internal read and write pointers. TheSCC's internal FIFOs are not affected when the external FIFOs are reset.The external FIFOs cannot be reset while they are enabled! FIFO reset commandswill be ignored if the external FIFOs are enabled.10.4.3 Reading current FIFO statusThe FIFO Status Register is a read-only register which always indicates the current statusof both the transmit and receive external FIFOs. Each FIFO can be checked for empty, full, andhalf-full (or more) status at any time. For details, see Table 12 on page 44.10.4.4 Controlling the FIFOsThe FIFO Control Register is a read-write register which can be used to reset either orboth the receive and transmit external FIFOs. Receive pattern detection and receive FIFOtimeout modes are also controlled with this register. For details, see Table 13 on page 45.10.5 Accessing the SCC while FIFOs are enabledThe SCC channel A and channel B control port registers are always accessible regardlessof whether the external FIFOs are enabled or disabled. While the FIFOs are enabled, SCC dataport accesses are redirected to the FIFOs. Access to the SCC's transmit or receive registers whilethe FIFOs are enabled is possible indirectly by using the control port and register 8. Any writesof SCC Write Register 8 (transmit buffer) or reads of SCC Read Register 8 (receive buffer) willbypass the external FIFOs.10.6 Receive pattern detectionThe external FIFOs are most useful in bit-synchronous operational modes because theSCC can generate a Special Condition interrupt when the closing flag of a bit-synchronous frameis received. This allows the SCC to run with per-character receive interrupts disabled whileDMA transfers occur between the SCC and external FIFOs.Byte-synchronous modes such as bisync, however, do not benefit from such a hardwareassist for detecting the end-of-frame condition. On the contrary, with byte-oriented protocols it isusually necessary to check each byte received against a table of special function codes (e.g.SYNC, PAD, SDI, STX, EDI, ETX, etc.) to determine where data and frames begin and end.Unless the frames are of a fixed length, it is therefore difficult to use DMA withbyte-synchronous modes. This would seem to preclude the use of the MPAP-100's externalFIFOs with byte-oriented protocols.