Quatech MPAP-100 User Manual

Also see for MPAP-100: Specifications User manual

Contents

Quatech MPAP-100 User Manual Manual pdf 55 page image

N/CN/CRxCLK (DTE)SYNCAN/CCDDGNDDSRCTSRTSRxDTxDCGND13121110987654321252423222120191817161514TM (OUTPUT)TxCLK (DTE)N/CN/CRLBK (OUTPUT)DTRN/CLLBK (OUTPUT)RxCLK (DCE)N/CTxCLK (DCE)RINGFigure 2 --- MPAP-100 Output ConnectorThe testing signals the DTE can generate are Local Loopback (LL) and Remote Loopback(RL). These signals are asserted with certain bits in the Communications Register. When a TestMode (TM) condition is received from the DCE, an interrupt can optionally be generated.19.1 SYNCA (pin 10)If EXTSYNC (bit 6) in the Communications Register is set to a logic 1, the SYNCAsignal from the connector is used to drive the active-low SYNC input of SCC channel A. Thesignal is inverted by the RS-232 receiver, so a positive voltage on pin 10 will assert SYNCA.The SCC must be specifically programmed to recognize external synchronization.19.2 RING (pin 22)If Card and Socket Services has set the SIGCHG bit in the PCMCIA Configuration StatusRegister to a logic 1, the RING signal is routed to the STSCHG line on the PCMCIA bus. Thesignal is inverted by the RS-232 receiver, so a positive voltage on pin 22 will assert STSCHG.Table 17 shows the pin configuration of the MPAP-100 DTE connector. The definitionsof the interchange circuits according to the RS-232-D standard can be found starting on page 52.SCC Pin or Register BitRS-232-DCircuitSignalFromDTEToDTEPin