Tait TB9100 Service Manual

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TB9100 Reciter Service Manual Network Circuitry 81© Tait Electronics Limited January 20065.8 Clock OscillatorBoth the MPC and DSP incorporate phase-locked loops to generate theirrespective high frequency clocks from a relatively low reference frequency.On the ASIF, separate reference frequencies can be used for the MPC andDSP: the MPC reference is supplied from an on-board 13MHz oscillator,while the DSP reference is supplied from either the 13MHz oscillator or thereciter 12.8MHz clock. The reciter 12.8MHz clock is normally used, sothat the DSP is operated in frequency synchronization with other reciterclocks.The 13.000MHz VCTXCO, Y200, provides a clipped sinewave output ofapproximately 1Vpp, which is amplified and buffered by inverter U800 toproduce an LVTTL clock signal. This is fed to the reference clock input ofthe MPC, RISC_CLK, via damping resistor R806 to minimize overshootand reflections, and preserve signal quality on the MPC clock input.To ensure that clipped sinewave is amplified symmetrically, preserving theduty cycle, the output of the VCTCXO is capacitively coupled into theinput of buffer U800. This device is then biased into the centre of its linearregion via its feedback resistor, R808.When the reciter 12.8MHz clock is used as the DSP PLL’s reference, theclock signal, DSP_CLK_IN, from the reciter is buffered by U801.This isthen passed to the DSP reference clock input, DSP_ CLK, via dampingresistor R806.For other applications, where the ASIF may not be attached to a reciter, theinternal 13.000MHz clock may be routed to the DSP reference clock. Inthis case, resistor R806 is omitted and resistor R805 installed.5.9 Power SupplyThe MPC and DSP require dual supply voltages, +1.8V and +1.6Vrespectively, for their core logic and +3.3V in each case for their I/O drivers.Most of the other devices on the board use +3.3V, except for the analogoutput and the general-purpose inputs, which use +6V supplies.The maximum operating current drains are 370mA from the +3.3V supply,180mA from the 1.8V supply, 120mA from the 1.6V supply and 12mA fromthe +6V supply. To minimize heat dissipation, all supplies are generated fromthe incoming +28V supply using switching regulators.The +3.3V and +1.8V supplies are generated by a dual-phase buckswitching converter, U900; this device incorporates two switch-modecontrollers, which are operated on opposite phases of a common clock.This arrangement forces the input current pulses from the two switchers toadd out of phase, thus reducing the peak ripple current drawn from theinput supply. The lower ripple current injects less noise back into the inputsupply, hence input filtering requirements are less onerous.