Xilinx 7 Series User Manual

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16 www.xilinx.com 7 Series DSP48E1 User GuideUG479 (v1.10) March 27, 2018Chapter 2: DSP48E1 Description and SpecificsArchitectural Highlights of the 7 Series FPGA DSP48E1 SliceThe 7 series FPGA DSP48E1 slice is functionally equivalent to the Virtex-6 FPGA DSP48E1.The 7 series FPGA DSP48E1 slice contains a pre-adder after the A register with a 25-bitinput vector called D. The D register can be used either as the pre-adder register or analternate input to the multiplier. The DSP48E1 specific features are highlighted inFigure 2-2. More detailed descriptions are found starting at Input Ports, page 29.X-Ref Target - Figure 2-2Figure 2-2: Hierarchical View of the 7 Series DSP48E1 Slice Input Registers and Pre-adderX17-Bit Shift17-Bit Shift0YZ100484818434830BCIN* ACIN*OPMODEPCIN*MULTSIGNIN*PCOUT*CARRYCASCOUT*MULTSIGNOUT*CREG/C Bypass/MaskCARRYCASCIN*CARRYINCARRYINSELA:BALUMODEBACBMPP PCMULT25 X 18PATTERNDETECTPATTERNBDETECTCARRYOUT4748483018PP5D 2525INMODEBCOUT* ACOUT*183043018Dual B RegisterDual A, D,and Pre-adder1+–UG369_c1_02_072209AD30 A1ACIN2525A MULTACOUTX MUX30302525 INMODE[2]INMODE[3]INMODE[0]INMODE[1]DA2ADCEA1 RSTACED RSTDCEA2 RSTACEAD RSTDB 18 B1BCINBCOUTX MUX181818INMODE[4]B MULTB2CEB1 RSTB CEB2 RSTBSend Feedback