Xilinx 7 Series User Manual

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7 Series DSP48E1 User Guide www.xilinx.com 29UG479 (v1.10) March 27, 2018Simplified DSP48E1 Slice OperationInput PortsA, B, C, CARRYIN, CARRYINSEL, OPMODE, BCIN, PCIN, ACIN, ALUMODE,CARRYCASCIN, MULTSIGNIN along with the corresponding clock enable inputs andreset inputs, are legacy ports. The D and INMODE ports are unique to the DSP48E1 slice.This section describes the input ports of the DSP48E1 slice in detail. The input ports of theDSP48E1 slice are highlighted in Figure 2-6.A, B, C, and D PortsThe DSP48E1 slice input data ports support many common DSP and math algorithms. TheDSP48E1 slice has four direct input data ports labeled A, B, C, and D. The A data port is30 bits wide, the B data port is 18 bits wide, the C data port is 48 bits wide, and the pre-adder D data port is 25 bits wide.OPMODE Register This optional pipeline register for the OPMODE control signal is selected byOPMODEREG, enabled by CECTRL, and reset synchronously by RSTCTRL.Output Registers This optional register for the P, OVERFLOW, UNDERFLOW, PATTERNDETECT,PATTERNDETECT, and CARRYOUT outputs is selected by PREG, enabled by CEP, andreset synchronously by RSTP. The same register also clocks out PCOUT,CARRYCASCOUT, and MULTSIGNOUT, which are the cascade outputs to the nextDSP48E1 slice.Table 2-4: Internal Register Descriptions (Cont’d)Register Description and Associated AttributeX-Ref Target - Figure 2-6Figure 2-6: Input Ports in the DSP48E1 SliceX17-Bit Shift17-Bit Shift0YZ10048481844830BCIN* ACIN*OPMODEPCIN*MULTSIGNIN*PCOUT*CARRYCASCOUT*MULTSIGNOUT*CARRYCASCIN*CARRYINCARRYINSELA:BALUMODEBACMPP PCMULT25 X 18CREG/C Bypass/MaskPATTERNDETECTPATTERNBDETECTCARRYOUTUG369_c1_06_0521094748483018PP*These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.1835D 2525INMODEACOUT*183043018Dual B RegisterDual A, D,and Pre-adder1Send Feedback