Xilinx 7 Series User Manual

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7 Series DSP48E1 User Guide www.xilinx.com 19UG479 (v1.10) March 27, 2018Architectural Highlights of the 7 Series FPGA DSP48E1 SliceDSP48E1 Tile and InterconnectTwo DSP48E1 slices and dedicated interconnect form a DSP48E1 tile (see Figure 2-3). TheDSP48E1 tiles stack vertically in a DSP48E1 column. The height of a DSP48E1 tile is thesame as five configurable logic blocks (CLBs) and also matches the height of one blockRAM. The block RAM in 7 series devices can be split into two 18K block RAMs. EachDSP48E1 slice aligns horizontally with an 18K block RAM. The 7 series devices have up to20 DSP48E1 columns.The 7 series devices offer from 10 to 3,600 DSP slices per device, yielding an impressiveprocessing power in the range of tens of GMAC/s up to thousands of GMAC/s (peak),enabling very intensive DSP applications. Table 2-1 shows the number of DSP48E1 slicesfor each device in the 7 series. Refer to the product tables on xilinx.com for information onthe Spartan-7, Artix-7, Kintex-7, and Virtex-7 families.X-Ref Target - Figure 2-3Figure 2-3: DSP48E1 Interconnect and Relative Dedicated Element SizesDSP48E1SliceDSP48E1SliceInterconnectUG479_c1_03_060910Table 2-1: Number of DSP48E1 Slices in 7 Series DevicesDevice Total DSP48E1 Slices perDeviceNumber of DSP48E1 Columnsper DeviceNumber of DSP48E1 Slicesper Column7S6 10 1 20(2)7S15 20 1 207S25 80 2 407S50 120 2 607S75 140 2 80 (2)7S100 160 2 807A12T 40 2 40 (2)7A15T 45 2 60 (2)7A25T 80 2 407A35T 90 2 60 (2)7A50T 120 2 607A75T 180 3 80(2)7A100T 240 3 807A200T 740 9 100 (1)7K70T 240 3 80Send Feedback