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24 www.xilinx.com 7 Series DSP48E1 User GuideUG479 (v1.10) March 27, 2018Chapter 2: DSP48E1 Description and SpecificsSimplified DSP48E1 Slice OperationThe math portion of the DSP48E1 slice consists of a 25-bit pre-adder, a 25-bit by 18-bit two’scomplement multiplier followed by three 48-bit datapath multiplexers (with outputs X, Y,and Z). This is followed by a three-input adder/subtracter or two-input logic unit (seeFigure 2-5). When using two-input logic unit, the multiplier cannot be used.The data and control inputs to the DSP48E1 slice feed the arithmetic and logic stages. TheA and B data inputs can optionally be registered one or two times to assist the constructionof different, highly pipelined, DSP application solutions. The D path and the AD path caneach be registered once. The other data inputs and the control inputs can be optionallyregistered once. Maximum frequency operation as specified in the data sheet is achievedby using pipeline registers. More detailed timing information is available in Chapter 3,DSP48E1 Design Considerations.In its most basic form, the output of the adder/subtracter/logic unit is a function of itsinputs. The inputs are driven by the upstream multiplexers, carry select logic, andmultiplier array.Equation 2-1 summarizes the combination of X, Y, Z, and CIN by the adder/subtracter. TheCIN, X multiplexer output, and Y multiplexer output are always added together. Thiscombined result can be selectively added to or subtracted from the Z multiplexer output.The second option is obtained by setting the ALUMODE to 0001.Adder/Sub Out = (Z ± (X + Y + CIN)) or (-Z + (X + Y + CIN) –1) Equation 2-1A typical use of the slice is where A and B inputs are multiplied and the result is added toor subtracted from the C register. More detailed operations based on control and datainputs are described in later sections. Selecting the multiplier function consumes bothX and Y multiplexer outputs to feed the adder. The two 43-bit partial products from themultiplier are sign extended to 48 bits before being sent to the adder/subtracter.When not using the first stage multiplier, the 48-bit, dual input, bitwise logic functionimplements AND, OR, NOT, NAND, NOR, XOR, and XNOR. The inputs to thesefunctions are A:B, C, P, or PCIN selected through the X and Z multiplexers, with theY multiplexer selecting either all 1s or all 0s depending on logic operation.The output of the adder/subtracter or logic unit feeds the pattern detector logic. Thepattern detector allows the DSP48E1 slice to support Convergent Rounding, CounterAutoreset when a count value has been reached, and Overflow/Underflow/Saturation inRSTINMODE In 1 Reset for the INMODE (control input) registers.RSTM In 1 Reset for the M (pipeline) register.RSTP In 1 Reset for the P (output) register.UNDERFLOW Out 1 Underflow indicator when used with the appropriate setting of thepattern detector.Notes:1. When these data ports are not in use and to reduce leakage power dissipation, the data port input signals must be tied High, the portinput register must be selected, and the CE and RST input control signals must be tied Low. An example of unused C portrecommended settings would be setting C[47:0] = all ones, CREG = 1, CEC = 0, and RSTC = 0.2. These signals are dedicated routing paths internal to the DSP48E1 column. They are not accessible via fabric routing resources.3. All signals are active High.Table 2-2: DSP48E1 Port Descriptions (Cont’d)Name Direction Bit Width DescriptionSend Feedback