Xilinx LogiCORE IP Spartan-6 Getting Started Manual
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Contents
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50 www.xilinx.com Spartan-6 FPGA GTP Transceiver Wizard v1.8UG546 (v1.8) December 14, 2010Chapter 5: Detailed Example DesignExample DesignThe example design that is delivered with the wrappers helps core designers understandhow to use the wrappers and GTP transceivers in a design. The example design is shownin Figure 5-1.The example design connects a frame generator and a frame checker to the wrapper. Theframe generator transmits an incrementing counting pattern while the frame checkermonitors the received data for correctness. The frame generator counting pattern is storedin block RAM. This pattern can be easily modified by altering the parameters in the framegenerator instantiation. The frame checker contains the same pattern in block RAM andcompares it with the received data. An error counter in the frame checker keeps a track ofhow many errors have occurred.If comma alignment is enabled, the comma character will be placed within the countingpattern. Similarly, if channel bonding is enabled, the channel bonding sequence would beinterspersed within the counting pattern. The frame check works by first scanning thereceived data for the START_OF_PACKET_CHAR. In 8B/10B designs, this is the commaalignment character. Once the START_OF_PACKET_CHAR has been found, the receiveddata will continuously be compared to the counting pattern stored in the block RAM ateach RXUSRCLK2 cycle. Once comparison has begun, if the received data ever fails tomatch the data in the block RAM, checking of receive data will immediately stop, an errorcounter will be incremented and the frame checker will return to searching for theSTART_OF_PACKET_CHAR.For 64B/66B and 64B/67B example designs, the frame generator has scrambler logic whilethe frame checker has descrambler and block synchronization logic.If the TX buffer is bypassed, the TX_SYNC module is instantiated in the example designand connected to the wrapper. The module performs the TX phase alignment procedureoutlined in the Spartan-6 FPGA GTP Transceivers User Guide. Similarly, if the RX buffer isbypassed, the RX_SYNC module is instantiated in the example design and connected toX-Ref Target - Figure 5-1Figure 5-1: Wrapper Block DiagramExample DesignTest BenchGSG546_05_01_071509WrapperGTPTransceiverPortsConfigurationParametersFRAME_GENFRAME_CHECK GTPA1_DUALTransceiverTile(s) |
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