Xilinx LogiCORE IP Spartan-6 manuals
LogiCORE IP Spartan-6
Table of contents
- revision history
- Table Of Contents
- Table Of Contents
- about this guide
- Typographical
- online document
- About the Wizard
- technical support
- Document
- installation and licensing
- Installing the Wizard
- Overview
- Setting Up the Project
- Setting the Project Options
- Generating the Core
- GTP Placement and Clocking
- Line Rate and Protocol Template
- B/10B Optional Ports
- Synchronization and Clocking
- RX Comma Alignment
- Preemphasis, Termination, and Equalization
- RX OOB, PRBS, and Loss of Sync
- RX PCI Express, SATA Features
- Channel Bonding, Clock Correction
- Clock Correction Sequence
- Summary
- Functional Simulation of the Example Design
- Using the ISE Simulator
- Directory and File Structure
- Directory and File Contents
- component name>/doc
- component name>/implement
- component name>/simulation
- Example Design
- Example Design Hierarchy
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