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Xilinx RocketIO User Manual

Also see for RocketIO: User guideUser guideUser guide

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Contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Chapter 1: Introduction
  6. RocketIO Features
  7. In This User Guide
  8. Basic Architecture and Capabilities
  9. Clock Synthesizer
  10. Clock and Data Recovery
  11. Transmit FIFO
  12. Receiver Termination
  13. Elastic and Transmitter Buffers
  14. Channel Bonding
  15. Transmitter Buffer
  16. List of Available Ports
  17. Primitive Attributes
  18. Modifiable Primitives
  19. Byte Mapping
  20. Clock Ratio
  21. Example 1: Two-Byte Clock
  22. Example 2: Four-Byte Clock
  23. Example 3: One-Byte Clock
  24. BREFCLK
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme
  27. Receiver Latency
  28. RocketIO Transceiver Instantiations
  29. RX_LOSS_OF_SYNC_FSM
  30. Vitesse Disparity Example
  31. Transmitting Vitesse Channel Bonding Sequence
  32. Status Signals
  33. B/10B Serial Output Format
  34. HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
  35. CRC Latency
  36. FIBRECHANNEL
  37. Channel Bonding (Channel-to-Channel Alignment)
  38. HDL Code Examples: Channel Bonding
  39. Other Important Design Notes
  40. bit Alignment Design
  41. VHDL
  42. Serial I/O Description
  43. Pre-emphasis Techniques
  44. Differential Receiver
  45. PCB Design Requirements
  46. Passive Filtering
  47. High-Speed Serial Trace Design
  48. Differential Trace Design
  49. AC and DC Coupling
  50. Reference Clock
  51. Simulation Models
  52. UCF Example
  53. MGT Package Pins
  54. Diagnostic Signals
  55. Timing Parameters
  56. Setup/Hold Times of Inputs Relative to Clock
  57. Timing Parameter Tables and Diagram
  58. Summary
  59. GT_AURORA_2
  60. GT_AURORA_4
  61. GT_CUSTOM
  62. GT_ETHERNET_1
  63. GT_ETHERNET_2
  64. GT_FIBRE_CHAN_1
  65. GT_FIBRE_CHAN_2
  66. GT_FIBRE_CHAN_4
  67. GT_INFINIBAND_1
  68. GT_INFINIBAND_2
  69. GT_INFINIBAND_4
  70. GT_XAUI_1
  71. GT_XAUI_2
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RocketIO
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