Manuals database logo
manualsdatabase
Your AI-powered manual search engine

Xilinx RocketIO manuals

RocketIO first page preview

RocketIO

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Schedule of Figures
  8. Schedule of Tables
  9. RocketIO Features
  10. For More Information
  11. Conventions
  12. Online Document
  13. Basic Architecture and Capabilities
  14. RocketIO Transceiver Instantiations
  15. List of Available Ports
  16. Primitive Attributes
  17. Modifiable Primitives
  18. Byte Mapping
  19. Clocking
  20. BREFCLK
  21. Clock Ratio
  22. Example 1a: Two-Byte Clock with DCM
  23. Example 1b: Two-Byte Clock without DCM
  24. Example 3: One-Byte Clock
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme with DCM
  27. RXRECCLK
  28. Reset/Power Down
  29. B/10B Encoding/Decoding
  30. Ports and Attributes
  31. TXCHARDISPVAL TXCHARDISPMODE
  32. TXCHARISK
  33. RXDISPERR
  34. Receiving Vitesse Channel Bonding Sequence
  35. B/10B Serial Output Format
  36. SERDES Alignment
  37. ENPCOMMAALIGN ENMCOMMAALIGN
  38. PCOMMA_DETECT MCOMMA_DETECT
  39. RXCHARISCOMMA
  40. Clock Correction
  41. CLK_CORRECT_USE
  42. CLK_COR_SEQ_*_
  43. Synchronization Logic
  44. RXCLKCORCNT
  45. RXLOSSOFSYNC
  46. Channel Bonding (Channel Alignment)
  47. Channel Bonding (Alignment) Operation
  48. CHAN_BOND_MODE
  49. CHAN_BOND_OFFSET CHAN_BOND_LIMIT
  50. CHBONDI CHBONDO
  51. CRC Generation
  52. TX_CRC_USE RX_CRC_USE
  53. CRC_START_OF_PACKET CRC_END_OF_PACKET
  54. Fabric Interface (Buffers)
  55. RX_BUFFER_USE
  56. RXPOLARITY TXINHIBIT
  57. other important design notes
  58. Other Important Design Notes
  59. bit Alignment Design
  60. VHDL
  61. Serial I/O Description
  62. Pre-emphasis Techniques
  63. Differential Receiver
  64. Clock and Data Recovery
  65. PCB Design Requirements
  66. Passive Filtering
  67. High-Speed Serial Trace Design
  68. Differential Trace Design
  69. AC and DC Coupling
  70. Reference Clock
  71. Powering the RocketIO Transceivers
  72. Simulation Models
  73. MGT Package Pins
  74. Timing Parameters
  75. Clock Pulse Width
  76. Valid Data Characters
  77. Valid Control Characters (K-Characters)
  78. Application Notes
  79. XAPP652: Word Alignment and SONET/SDH Deframing
  80. RocketIO Transceivers
  81. XAPP687: 64B/66B Encoder/Decoder
  82. White Papers
  83. Index
  84. Receive Data Path 32-bit Alignment
RocketIO first page preview

RocketIO

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Schedule of Figures
  8. Schedule of Tables
  9. RocketIO Features
  10. For More Information
  11. Conventions
  12. Online Document
  13. Basic Architecture and Capabilities
  14. RocketIO Transceiver Instantiations
  15. List of Available Ports
  16. Primitive Attributes
  17. Modifiable Primitives
  18. Byte Mapping
  19. Clocking
  20. BREFCLK
  21. Clock Ratio
  22. Example 1a: Two-Byte Clock with DCM
  23. Example 1b: Two-Byte Clock without DCM
  24. Example 3: One-Byte Clock
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme with DCM
  27. RXRECCLK
  28. Data Path Latency
  29. B/10B Encoding/Decoding
  30. Ports and Attributes
  31. TXCHARDISPVAL TXCHARDISPMODE
  32. TXCHARISK
  33. RXDISPERR
  34. Receiving Vitesse Channel Bonding Sequence
  35. B/10B Serial Output Format
  36. SERDES Alignment
  37. ENPCOMMAALIGN ENMCOMMAALIGN
  38. RocketIO™ Transceiver User Guide www.xilinx.com
  39. PCOMMA_DETECT MCOMMA_DETECT
  40. RXCHARISCOMMA
  41. Clock and Data Recovery
  42. CLK_CORRECT_USE
  43. RX_BUFFER_USE
  44. CLK_COR_SEQ_LEN
  45. Synchronization Logic
  46. RX_LOS_INVALID_INCR RX_LOS_THRESHOLD
  47. Channel Bonding (Channel Alignment)
  48. Channel Bonding (Alignment) Operation
  49. CHAN_BOND_MODE
  50. CHAN_BOND_OFFSET CHAN_BOND_LIMIT
  51. CHBONDDONE
  52. CRC (Cyclic Redundancy Check)
  53. CRC Latency
  54. CRC_START_OF_PACKET CRC_END_OF_PACKET
  55. TXFORCECRCERR TX_CRC_FORCE_VALUE
  56. TXBUFERR
  57. TERMINATION_IMP
  58. Other Important Design Notes
  59. bit Alignment Design
  60. VHDL
  61. Serial I/O Description
  62. Pre-emphasis Techniques
  64. Differential Receiver
  66. PCB Design Requirements
  67. Termination Voltage
  68. Passive Filtering
  69. High-Speed Serial Trace Design
  70. Differential Trace Design
  71. AC and DC Coupling
  72. Reference Clock
  73. Powering the RocketIO Transceivers
  74. Simulation Models
  75. MGT Package Pins
  76. Timing Parameters
  77. Clock Pulse Width
  78. Valid Data Characters
  79. Valid Control Characters (K-Characters)
  80. Application Notes
  81. XAPP649: SONET Rate Conversion in Virtex-II Pro Devices
  82. XAPP661: RocketIO Transceiver Bit-Error Rate Tester
  83. RocketIO Transceiver
  84. Multi-Gigabit Transceivers
  85. Characterization Summary
  86. Embedded RocketIO Transceivers
  87. Index
RocketIO first page preview

RocketIO

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. about this guide
  8. related information
  9. port and attribute names
  10. basic architecture and capabilities
  11. hdl code examples
  12. primitive attributes
  13. byte mapping
  14. Top-Level Architecture
  15. operation modes
  16. Dynamic Signals
  17. bus interface
  18. B/10B
  19. Encoder
  20. Decoder
  21. rxcharisk and rxrundisp
  22. vitesse disparity example
  23. Comma Detection
  24. Alignment
  25. B/66B
  26. Scrambler
  27. Gearbox
  28. Block Sync
  29. clock correction
  30. clock correction sequences
  31. channel bonding
  32. status indication
  33. event indication
  34. Clock Domain Architecture
  35. Clock Ports
  36. use models
  39. Supported Use Models for Each PMA Mode
  40. clock dependency
  41. data path latency
  42. Resets and Power Down
  43. Serial I/O Description
  44. Output Swing and Emphasis
  45. DC Coupled
  46. AC Coupled
  47. differential receiver
  48. clock and data recovery
  49. Receive Equalization
  50. Low Frequency Boosting
  51. Mid Frequency Boosting
  52. High Frequency Boosting
  53. Simulation Transmitter Emphasis and Receiver Equalization Settings
  54. pcb design requirements
  55. passive filtering
  56. routing serial traces
  57. differential trace design
  58. ac and dc coupling
  59. other important design notes
  60. reference clock
  61. PMA Initialization
  62. model considerations
  63. mgt package pins
  64. Diagnostic Signals
  65. parallel loopback
  66. timing parameters
  67. Timing Diagram and Timing Parameter Tables
  68. Appendix C, "PMA Attribute Programming Bus
  69. Valid Data and Control Characters
  70. interface description
  71. memory map
  72. Register Definition
  73. TXBUSWID
  74. IBOOST
  75. TXVCOGAIN
  76. PRDRVOFF
  77. TXDIGSW
  78. RXLOOPFILTERC[1:0]
  79. RXLOOPFILTERR[2:0]
  80. RXVCOGAIN
  81. RXVSELCP[1:0]
  82. RXCPGAIN
  83. RXFER[9:0]
  84. TXDIGEN
  85. TXDRVEN
  86. primary differences
  87. Figure D-2
  88. High-Speed Serial I/O Termination
  89. Migration Differences
  90. Channel Bonding
  92. Transmission Lines
  93. Package to PCB Launch
  94. Appendix F: Modifiable Attributes
  103. application notes
  104. characterization reports
  105. Index
  106. Table Of Contents
RocketIO first page preview

RocketIO

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Chapter 1: Introduction
  6. RocketIO Features
  7. In This User Guide
  8. Basic Architecture and Capabilities
  9. Clock Synthesizer
  10. Clock and Data Recovery
  11. Transmit FIFO
  12. Receiver Termination
  13. Elastic and Transmitter Buffers
  14. Channel Bonding
  15. Transmitter Buffer
  16. List of Available Ports
  17. Primitive Attributes
  18. Modifiable Primitives
  19. Byte Mapping
  20. Clock Ratio
  21. Example 1: Two-Byte Clock
  22. Example 2: Four-Byte Clock
  23. Example 3: One-Byte Clock
  24. BREFCLK
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme
  27. Receiver Latency
  28. RocketIO Transceiver Instantiations
  29. RX_LOSS_OF_SYNC_FSM
  30. Vitesse Disparity Example
  31. Transmitting Vitesse Channel Bonding Sequence
  32. Status Signals
  33. B/10B Serial Output Format
  34. HDL Code Examples: Transceiver Bypassing of 8B/10B Encoding
  35. CRC Latency
  36. FIBRECHANNEL
  37. Channel Bonding (Channel-to-Channel Alignment)
  38. HDL Code Examples: Channel Bonding
  39. Other Important Design Notes
  40. bit Alignment Design
  41. VHDL
  42. Serial I/O Description
  43. Pre-emphasis Techniques
  44. Differential Receiver
  45. PCB Design Requirements
  46. Passive Filtering
  47. High-Speed Serial Trace Design
  48. Differential Trace Design
  49. AC and DC Coupling
  50. Reference Clock
  52. Simulation Models
  53. UCF Example
  54. MGT Package Pins
  55. Diagnostic Signals
  56. Timing Parameters
  57. Setup/Hold Times of Inputs Relative to Clock
  58. Timing Parameter Tables and Diagram
  59. Summary
  60. GT_AURORA_2
  61. GT_AURORA_4
  62. GT_CUSTOM
  63. GT_ETHERNET_1
  64. GT_ETHERNET_2
  65. GT_FIBRE_CHAN_1
  66. GT_FIBRE_CHAN_2
  67. GT_FIBRE_CHAN_4
  68. GT_INFINIBAND_1
  69. GT_INFINIBAND_2
  70. GT_INFINIBAND_4
  71. GT_XAUI_1
  72. GT_XAUI_2
Related products
RocketIO XC2VP2RocketIO XC2VP7RocketIO XC2VP4RocketIO XC2VP70RocketIO XC2VP40RocketIO XC2VP20RocketIO XC2VP30RocketIO XC2VP50RocketIO XC2VP100Virtex-4 RocketIO
Xilinx categories
Motherboard
Computer Hardware
Controller
I/O Systems
Transceiver
Microcontrollers
Network Card
Cables and connectors
PCI Card
Video Card
More Xilinx categories
Manuals database logo
manualsdatabase
Your AI-powered manual search engine