Xilinx ZCU102 User Manual
Also see for ZCU102: ManualGetting Started Quick GuideTutorialSoftware Install and Board SetupQuick start guide
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ZCU102 Evaluation Board User Guide www.xilinx.com 119UG1182 (v1.2) March 20, 2017Appendix B: Master Constraints File Listing#Other net PACKAGE_PIN AN19 - DDR4_SODIMM_DQS0_C Bank 504 - PS_DDR_DQS_N0#Other net PACKAGE_PIN AN22 - DDR4_SODIMM_DQS1_C Bank 504 - PS_DDR_DQS_N1#Other net PACKAGE_PIN AJ19 - DDR4_SODIMM_DQS2_C Bank 504 - PS_DDR_DQS_N2#Other net PACKAGE_PIN AH23 - DDR4_SODIMM_DQS3_C Bank 504 - PS_DDR_DQS_N3#Other net PACKAGE_PIN AH29 - DDR4_SODIMM_DQS4_C Bank 504 - PS_DDR_DQS_N4#Other net PACKAGE_PIN AE29 - DDR4_SODIMM_DQS5_C Bank 504 - PS_DDR_DQS_N5#Other net PACKAGE_PIN AK32 - DDR4_SODIMM_DQS6_C Bank 504 - PS_DDR_DQS_N6#Other net PACKAGE_PIN AE33 - DDR4_SODIMM_DQS7_C Bank 504 - PS_DDR_DQS_N7#Other net PACKAGE_PIN AN33 - DDR4_SODIMM_DQS8_C Bank 504 - PS_DDR_DQS_N8#Other net PACKAGE_PIN AN18 - DDR4_SODIMM_DQS0_T Bank 504 - PS_DDR_DQS_P0#Other net PACKAGE_PIN AN21 - DDR4_SODIMM_DQS1_T Bank 504 - PS_DDR_DQS_P1#Other net PACKAGE_PIN AH19 - DDR4_SODIMM_DQS2_T Bank 504 - PS_DDR_DQS_P2#Other net PACKAGE_PIN AH22 - DDR4_SODIMM_DQS3_T Bank 504 - PS_DDR_DQS_P3#Other net PACKAGE_PIN AH28 - DDR4_SODIMM_DQS4_T Bank 504 - PS_DDR_DQS_P4#Other net PACKAGE_PIN AE28 - DDR4_SODIMM_DQS5_T Bank 504 - PS_DDR_DQS_P5#Other net PACKAGE_PIN AJ32 - DDR4_SODIMM_DQS6_T Bank 504 - PS_DDR_DQS_P6#Other net PACKAGE_PIN AE32 - DDR4_SODIMM_DQS7_T Bank 504 - PS_DDR_DQS_P7#Other net PACKAGE_PIN AN32 - DDR4_SODIMM_DQS8_T Bank 504 - PS_DDR_DQS_P8#Other net PACKAGE_PIN AM30 - DDR4_SODIMM_ODT0 Bank 504 - PS_DDR_ODT0#Other net PACKAGE_PIN AJ26 - DDR4_SODIMM_ODT1 Bank 504 - PS_DDR_ODT1#Other net PACKAGE_PIN AF20 - DDR4_SODIMM_PARITY Bank 504 - PS_DDR_PARITY#DDR4 COMPONENT 16-BIT U2set_property PACKAGE_PIN AM8 [get_ports "DDR4_A0"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"]set_property PACKAGE_PIN AM9 [get_ports "DDR4_A1"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"]set_property PACKAGE_PIN AP8 [get_ports "DDR4_A2"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"]set_property PACKAGE_PIN AN8 [get_ports "DDR4_A3"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"]set_property PACKAGE_PIN AJ10 [get_ports "DDR4_A5"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"]set_property PACKAGE_PIN AP9 [get_ports "DDR4_A6"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"]set_property PACKAGE_PIN AN9 [get_ports "DDR4_A7"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"]set_property PACKAGE_PIN AP10 [get_ports "DDR4_A8"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"]set_property PACKAGE_PIN AP11 [get_ports "DDR4_A9"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"]set_property PACKAGE_PIN AM10 [get_ports "DDR4_A10"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"]set_property PACKAGE_PIN AL10 [get_ports "DDR4_A11"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"]set_property PACKAGE_PIN AM11 [get_ports "DDR4_A12"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"]set_property PACKAGE_PIN AL11 [get_ports "DDR4_A13"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"]set_property PACKAGE_PIN AJ7 [get_ports "DDR4_A14_WE_B"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"]set_property PACKAGE_PIN AL5 [get_ports "DDR4_A15_CAS_B"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"]set_property PACKAGE_PIN AJ9 [get_ports "DDR4_A16_RAS_B"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"]set_property PACKAGE_PIN AK12 [get_ports "DDR4_BA0"]set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"]set_property PACKAGE_PIN AJ12 [get_ports "DDR4_BA1"]Send Feedback |
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