Xilinx ZCU104 User Manual

Also see for Zynq UltraScale+ ZCU104: Quick start guide GUI Tutorial

Contents

Xilinx ZCU104 User Manual Manual pdf 44 page image

ZCU104 Board User Guide 44UG1267 (v1.1) October 9, 2018 www.xilinx.comChapter 3: Board Component DescriptionsClock GenerationThe ZCU104 board provides an IDT8T49N287 FemtoClock® NG octal universal frequencytranslator (U182) clock generator. Table 3-12 lists the frequency for each clock.Table 3-13 lists the connectivity for each clock.Table 3-12: Clock SourcesClock (Net) Name Frequency IDT8T49N287 U182Clock OutputHDMI_DRU_CLOCK 156.25 MHz Q0PS_REF_CLK 33.33 MHz Q1GTR_REF_CLK_USB3 26 MHz Q2GTR_REF_CLK_DP 27 MHz Q3CLK_300_P 300 MHz Q4GTR_REF_CLK_SATA 125 MHz Q5CLK_125 125 MHz Q6Table 3-13: Clock Connections, Source to XCZU7EV MPSoCClock Source Pin Net Name I/O Standard XCZU7EV (U1) PinU182.48 HDMI_DRU_CLOCK_P (2) U10U182.47 HDMI_DRU_CLOCK_N (2) U9U182.44 PS_REF_CLK LVCMOS18 (1) R24U182.27 GTR_REF_CLK_USB3_P (2) M27U182.28 GTR_REF_CLK_USB3_N (2) M28U182.23 GTR_REF_CLK_DP_P (2) M31U182.24 GTR_REF_CLK_DP_N (2) M32U182.40 CLK_300_C_P (2) AH12U182.39 CLK_300_C_N (2) AJ12U182.37 GTR_REF_CLK_SATA_P (2) P27U182.36 GTR_REF_CLK_SATA_N (2) P28U182.34 CLK_125_P LVDS H11U182.33 CLK_125_N LVDS G11Notes:1. U1 XCU7EV Bank 503 supports LVCMOS level inputs.2. U1 MGT (I/O standards do not apply).Send Feedback