Xilinx ZCU104 User Manual

Also see for Zynq UltraScale+ ZCU104: Quick start guide GUI Tutorial

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Xilinx ZCU104 User Manual Manual pdf 76 page image

ZCU104 Board User Guide 76UG1267 (v1.1) October 9, 2018 www.xilinx.comChapter 3: Board Component DescriptionsFPGA Mezzanine Card Interface[Figure 2-1, callout 25]The ZCU104 evaluation board supports the VITA 57.1 FPGA mezzanine card (FMC)specification [Ref 19] by implementing the LPC connector (J5). LPC connectors use a 10 x 40form factor, partially populated with 160 pins. The connector is keyed so that a mezzaninecard, when installed in the FMC LPC connector on the ZCU104 evaluation board, faces awayfrom the boardFMC LPC Connector J5[Figure 2-1, callout 25]The FMC connector at J5 implements the full FMC LPC connectivity:• 68 single-ended, or 34 differential user-defined pairs (34 LA pairs: LA[00:33])• One GTH transceiver DP differential pair• Two GBTCLK differential clocks• 61 ground and 10 power connectionsThe ZCU104 board FMC VADJ voltage for LPC connector J5 is determined by theIRPS5401MTRPBF U180 voltage regulator described in Board Power System, page 83. Validvalues for the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V. The LPC J5 connections to XCZU7EVU1 are shown in Table 3-29 and Table 3-30.P27 PS_MGTREFCLK1P GTR_REF_CLK_SATA_C_P (1) 37 Q58T49N287 U182P28 PS_MGTREFCLK1N GTR_REF_CLK_SATA_C_N (1) 36 NQ5M27 PS_MGTREFCLK2P GTR_REF_CLK_USB3_C_P (1) 27 Q2M28 PS_MGTREFCLK2N GTR_REF_CLK_USB3_C_N (1) 28 NQ2M31 PS_MGTREFCLK3P GTR_REF_CLK_DP_C_P (1) 23 Q3M32 PS_MGTREFCLK3N GTR_REF_CLK_DP_C_N (1) 23 NQ3Notes:1. Series capacitor coupled.2. MGT connections I/O standard not applicable.Table 3-28: PS-GTR Bank 505 Interface Connections (Cont’d)XCZU7EV(U1) Pin XCZU7EV Pin Name Schematic Net Name (2) Connected ToPin No. Pin Name DeviceSend Feedback