Manuals database logo
manualsdatabase
Your AI-powered manual search engine

Xilinx RocketIO XC2VP4 manuals

RocketIO XC2VP4 first page preview

RocketIO XC2VP4

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Schedule of Figures
  8. Schedule of Tables
  9. RocketIO Features
  10. For More Information
  11. Conventions
  12. Online Document
  13. Basic Architecture and Capabilities
  14. RocketIO Transceiver Instantiations
  15. List of Available Ports
  16. Primitive Attributes
  17. Modifiable Primitives
  18. Byte Mapping
  19. Clocking
  20. BREFCLK
  21. Clock Ratio
  22. Example 1a: Two-Byte Clock with DCM
  23. Example 1b: Two-Byte Clock without DCM
  24. Example 3: One-Byte Clock
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme with DCM
  27. RXRECCLK
  28. Reset/Power Down
  29. B/10B Encoding/Decoding
  30. Ports and Attributes
  31. TXCHARDISPVAL TXCHARDISPMODE
  32. TXCHARISK
  33. RXDISPERR
  34. Receiving Vitesse Channel Bonding Sequence
  35. B/10B Serial Output Format
  36. SERDES Alignment
  37. ENPCOMMAALIGN ENMCOMMAALIGN
  38. PCOMMA_DETECT MCOMMA_DETECT
  39. RXCHARISCOMMA
  40. Clock Correction
  41. CLK_CORRECT_USE
  42. CLK_COR_SEQ_*_
  43. Synchronization Logic
  44. RXCLKCORCNT
  45. RXLOSSOFSYNC
  46. Channel Bonding (Channel Alignment)
  47. Channel Bonding (Alignment) Operation
  48. CHAN_BOND_MODE
  49. CHAN_BOND_OFFSET CHAN_BOND_LIMIT
  50. CHBONDI CHBONDO
  51. CRC Generation
  52. TX_CRC_USE RX_CRC_USE
  53. CRC_START_OF_PACKET CRC_END_OF_PACKET
  54. Fabric Interface (Buffers)
  55. RX_BUFFER_USE
  56. RXPOLARITY TXINHIBIT
  57. other important design notes
  58. Other Important Design Notes
  59. bit Alignment Design
  60. VHDL
  61. Serial I/O Description
  62. Pre-emphasis Techniques
  63. Differential Receiver
  64. Clock and Data Recovery
  65. PCB Design Requirements
  66. Passive Filtering
  67. High-Speed Serial Trace Design
  68. Differential Trace Design
  69. AC and DC Coupling
  70. Reference Clock
  71. Powering the RocketIO Transceivers
  72. Simulation Models
  73. MGT Package Pins
  74. Timing Parameters
  75. Clock Pulse Width
  76. Valid Data Characters
  77. Valid Control Characters (K-Characters)
  78. Application Notes
  79. XAPP652: Word Alignment and SONET/SDH Deframing
  80. RocketIO Transceivers
  81. XAPP687: 64B/66B Encoder/Decoder
  82. White Papers
  83. Index
  84. Receive Data Path 32-bit Alignment
RocketIO XC2VP4 first page preview

RocketIO XC2VP4

Brand: Xilinx | Category: Transceiver
Table of contents
  1. user guide
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Schedule of Figures
  8. Schedule of Tables
  9. RocketIO Features
  10. For More Information
  11. Conventions
  12. Online Document
  13. Basic Architecture and Capabilities
  14. RocketIO Transceiver Instantiations
  15. List of Available Ports
  16. Primitive Attributes
  17. Modifiable Primitives
  18. Byte Mapping
  19. Clocking
  20. BREFCLK
  21. Clock Ratio
  22. Example 1a: Two-Byte Clock with DCM
  23. Example 1b: Two-Byte Clock without DCM
  24. Example 3: One-Byte Clock
  25. Half-Rate Clocking Scheme
  26. Multiplexed Clocking Scheme with DCM
  27. RXRECCLK
  28. Data Path Latency
  29. B/10B Encoding/Decoding
  30. Ports and Attributes
  31. TXCHARDISPVAL TXCHARDISPMODE
  32. TXCHARISK
  33. RXDISPERR
  34. Receiving Vitesse Channel Bonding Sequence
  35. B/10B Serial Output Format
  36. SERDES Alignment
  37. ENPCOMMAALIGN ENMCOMMAALIGN
  38. RocketIO™ Transceiver User Guide www.xilinx.com
  39. PCOMMA_DETECT MCOMMA_DETECT
  40. RXCHARISCOMMA
  41. Clock and Data Recovery
  42. CLK_CORRECT_USE
  43. RX_BUFFER_USE
  44. CLK_COR_SEQ_LEN
  45. Synchronization Logic
  46. RX_LOS_INVALID_INCR RX_LOS_THRESHOLD
  47. Channel Bonding (Channel Alignment)
  48. Channel Bonding (Alignment) Operation
  49. CHAN_BOND_MODE
  50. CHAN_BOND_OFFSET CHAN_BOND_LIMIT
  51. CHBONDDONE
  52. CRC (Cyclic Redundancy Check)
  53. CRC Latency
  54. CRC_START_OF_PACKET CRC_END_OF_PACKET
  55. TXFORCECRCERR TX_CRC_FORCE_VALUE
  56. TXBUFERR
  57. TERMINATION_IMP
  58. Other Important Design Notes
  59. bit Alignment Design
  60. VHDL
  61. Serial I/O Description
  62. Pre-emphasis Techniques
  64. Differential Receiver
  66. PCB Design Requirements
  67. Termination Voltage
  68. Passive Filtering
  69. High-Speed Serial Trace Design
  70. Differential Trace Design
  71. AC and DC Coupling
  72. Reference Clock
  73. Powering the RocketIO Transceivers
  74. Simulation Models
  75. MGT Package Pins
  76. Timing Parameters
  77. Clock Pulse Width
  78. Valid Data Characters
  79. Valid Control Characters (K-Characters)
  80. Application Notes
  81. XAPP649: SONET Rate Conversion in Virtex-II Pro Devices
  82. XAPP661: RocketIO Transceiver Bit-Error Rate Tester
  83. RocketIO Transceiver
  84. Multi-Gigabit Transceivers
  85. Characterization Summary
  86. Embedded RocketIO Transceivers
  87. Index
Related products
RocketIO XC2VP40RocketIO XC2VP7RocketIO XC2VP2RocketIO XC2VP30RocketIO XC2VP70RocketIO XC2VP20RocketIO XC2VP50RocketIO XC2VP100RocketIOVirtex-4 RocketIO
Xilinx categories
Motherboard
Computer Hardware
Controller
I/O Systems
Transceiver
Microcontrollers
Network Card
Cables and connectors
PCI Card
Video Card
More Xilinx categories
Manuals database logo
manualsdatabase
Your AI-powered manual search engine