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National Instruments MIO-64XE-10 manuals

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MIO-64XE-10

Brand: National Instruments | Category: I/O Systems
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. General Characteristics
  8. Functional Overview
  9. Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram
  10. Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram
  11. Figure 2-4. PCI-6032E and PCI-6033E Block Diagram
  12. Figure 2-5. PCI-MIO-16XE-50 Block Diagram
  13. PCI Interface Circuitry
  14. Analog Input and Timing Circuitry
  15. Analog Input Circuitry
  16. Table 2-1. PGIA Gain Set Verses Board
  17. Single-Read Timing
  18. Data Acquisition Sequence Timing
  19. Figure 2-9. Timing of Scan in Example 1
  20. Figure 2-10. Multirate Scanning of Two Channels
  21. Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate
  22. Figure 2-14. Multirate Scanning without Ghost
  23. Posttrigger and Pretrigger Acquisition
  24. Analog Triggering
  25. Analog Output and Timing Circuitry
  26. Analog Output Circuitry
  27. Single-Point Output
  28. Waveform Generation
  29. Digital I/O Circuitry
  30. RTSI Bus Interface Circuitry
  31. Figure 2-19. RTSI Bus Interface Circuitry Block Diagram
  32. Register Map
  33. Table 3-1. PCI E Series Register Map
  34. Register Sizes
  35. Misc Command Register
  36. Status Register
  37. Analog Input Register Group
  38. ADC FIFO Data Register
  39. Configuration Memory Low Register
  40. Table 3-3. PGIA Gain Selection
  41. Configuration Memory High Register
  42. Table 3-4. Calibration Channel Assignments
  43. Table 3-5. Differential Channel Assignments
  44. Table 3-7. Referenced Single-Ended Channel Assignments
  45. Analog Output Register Group
  46. AO Configuration Register
  47. DAC FIFO Data Register
  48. DAC0 Direct Data Register
  49. DAC1 Direct Data Register
  50. DMA Control Register Group
  51. AI AO Select Register
  52. G0 G1 Select Register
  53. DAQ-STC Register Group
  54. PCl Local Bus
  55. PCI Initialization for the IBM Compatible System
  56. Re-mapping the PCI E Series Board
  57. PCI Initialization for the Macintosh
  58. Windowing Registers
  59. Digital I/O
  60. Analog Input
  61. Example 1
  62. Example 2
  63. Example 3
  64. Example Program
  65. Example 4
  66. Programming the MITE for Different DMA Transfers
  67. Example 5
  68. Example 6
  69. Example 7
  70. Example 8
  71. Example 9
  72. Analog Output
  78. General-Purpose Counter/Timer
  81. RTSI Trigger Lines Programming Considerations
  82. Figure 4-1. Analog Trigger Structure
  83. Interrupt Programming
  84. DMA Programming
  85. The Link Chaining Mode for DMA Transfer
  86. Figure 4-3. DMA Link Chaining Mode Structure
  87. About the EEPROM
  88. Figure 5-1. EEPROM Read Timing
  89. Table 5-1. PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6071E EEPROM Map
  90. Table 5-2. PCI-MIO-16XE-50 EEPROM Map
  91. Table 5-3. PCI-MIO-16XE-10, PCI-6031E, PCI-6032E and PCI-6033E EEPROM Map
  92. Table 5-4. PCI-6023E EEPROM Map
  93. Table 5-5. PCI-6024E and PCI-6025E EEPROM Map
  94. Table 5-6. PCI-6052E EEPROM Map
  95. Calibration DACs
  96. Figure 5-2. Calibration AC Write Timing
  97. NI-DAQ Calibration Function
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AI-64XE-10MIO-64E-1PCI-MIO-16XE-10AT-MIO-16AT-MIO-16DPCI-MIO-16XE-50PCI-MIO-16E-1PCI-MIO-16E-4PC-TIO-10AI-16XE-10
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