National Instruments PCI E Series Programmer's Manual

Also see for DAQ PCI-6023E: User manual

Contents

National Instruments PCI E Series Programmer's Manual Manual pdf 7 page image

ContentsPCI E Series RLPMviii ©National Instruments CorporationFiguresFigure 2-1. PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E Block Diagram ..... 2-1Figure 2-2. PCI-MIO-16XE-10, PCI-6052E, and PCI-6031E Block Diagram ......... 2-2Figure 2-3. PCI-6023E, PCI-6024E, and PCI-6025E Block Diagram ...................... 2-3Figure 2-4. PCI-6032E and PCI-6033E Block Diagram ........................................... 2-4Figure 2-5. PCI-MIO-16XE-50 Block Diagram........................................................ 2-5Figure 2-6. PCI Bus Interface Circuitry Block Diagram ........................................... 2-7Figure 2-7. Analog Input and Data Acquisition Circuitry Block Diagram ............... 2-8Figure 2-8. ADC Timing ........................................................................................... 2-12Figure 2-9. Timing of Scan in Example 1 ................................................................. 2-14Figure 2-10. Multirate Scanning of Two Channels ..................................................... 2-15Figure 2-11. Multirate Scanning of Two Channels with 1:x Sampling Rate............... 2-15Figure 2-12. Multirate Scanning of Two Channels with 3:1:1 Sampling Rate ........... 2-16Figure 2-13. Multirate Scanning of Three Channels with 4:2:1 Sampling Rate ......... 2-16Figure 2-14. Multirate Scanning without Ghost .......................................................... 2-17Figure 2-15. Occurrences of Conversion on Channel 1 in Example 3 ........................ 2-17Figure 2-16. Successive Scans Using Ghost................................................................ 2-17Figure 2-17. Analog Output Circuitry Block Diagram................................................ 2-20Figure 2-18. DAQ-STC Counter Diagram .................................................................. 2-24Figure 2-19. RTSI Bus Interface Circuitry Block Diagram ........................................ 2-26Figure 4-1. Analog Trigger Structure ........................................................................ 4-54Figure 4-2. DMA Structure........................................................................................ 4-57Figure 4-3. DMA Link Chaining Mode Structure ..................................................... 4-59Figure 5-1. EEPROM Read Timing .......................................................................... 5-2Figure 5-2. Calibration AC Write Timing ................................................................. 5-16TablesTable 2-1. PGIA Gain Set Verses Board ............................................................... 2-9Table 2-2. Analog Input Configuration Memory .................................................. 2-18Table 3-1. PCI E Series Register Map .................................................................. 3-2Table 3-2. PCI E Series Windowed Register Map ................................................. 3-3Table 3-3. PGIA Gain Selection............................................................................. 3-10Table 3-4. Calibration Channel Assignments......................................................... 3-12Table 3-5. Differential Channel Assignments ........................................................ 3-13Table 3-6. Nonreferenced Single-Ended Channel Assignments ........................... 3-13Table 3-7. Referenced Single-Ended Channel Assignments.................................. 3-14Table 3-8. Auxiliary Channel Assignments ........................................................... 3-15Table 3-9. Channel Assignments............................................................................ 3-15