Chapter 2 Theory of OperationPCI E Series RLPM2-12 ©National Instruments Corporationappropriate bit in a register in the PCI E Series register set. Any one ofthese operations will generate the timing shown in Figure 2-8.Figure 2-8. ADC TimingWhen SHIFTIN* shifts the ADC value into the ADC FIFO buffer, theAI_FIFO_Empty_St bit in the status register is cleared, which indicatesthat valid data is available to be read. Single conversion timing of this typeis appropriate for reading channel data on an ad hoc basis. However, if youneed a sequence of conversions, the time interval between successiveconversions is not constant because it relies on the software to generate theconversions. For finely timed conversions that require triggering andgating, you must program the boards to automatically generate timedsignals that initiate and gate conversions. This is known as a dataacquisition (DAQ) sequence.Data Acquisition Sequence TimingThe following counters are used for a data acquisition sequence:• Scan interval (SI) 24 bits• Sample interval (SI2) 16 bits• Divide by (DIV) 16 bits• Scan counter (SC) 24 bitsThis section presents a concise summary of only the most importantfeatures of your board. For a complete description of all the analog inputmodes and features of the PCI E Series boards, refer to the DAQ-STCTechnical Reference Manual.The most basic timing signal in the analog input model is the CONVERT*signal. A group of precisely timed CONVERT* pulses is a SCAN. Thesequence of channels selected in each conversion in a SCAN isprogrammed in the configuration memory prior to starting the operation.The SI2 counter is a 16-bit counter in the DAQ-STC. This counterCONVERT*ADC_BUSY*SHIFTIN*
