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PD789860

Brand: NEC | Category: Microcontrollers
Table of contents
  1. User's Manual U14826EJ5V0UD
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Features
  14. Quality Grade
  15. K/0S Series Lineup
  16. Block Diagram
  17. Overview of Functions
  19. Pin Configuration (Top View)
  23. CHAPTER 3 PIN FUNCTIONS
  24. Description of Pin Functions
  25. IC (mask ROM version only)
  26. Pin I/O Circuits and Recommended Connection of Unused Pins
  27. CHAPTER 4 CPU ARCHITECTURE
  28. Internal program memory space
  29. Special function register (SFR) area
  30. Processor Registers
  31. Stack Pointer Configuration
  32. General-purpose registers
  33. Special function registers (SFRs)
  34. Special Function Registers
  35. Instruction Address Addressing
  36. Immediate addressing
  37. Register addressing
  38. Operand Address Addressing
  39. Short direct addressing
  40. Special function register (SFR) addressing
  42. Register indirect addressing
  43. Based addressing
  44. CHAPTER 5 EEPROM (DATA MEMORY)
  45. Format of EEPROM Write Control Register 10
  46. Notes for EEPROM Writing
  47. CHAPTER 6 PORT FUNCTIONS
  48. Port 0
  49. Port 2
  50. Port 4
  51. Port Function Control Registers
  52. Operation of Port Functions
  53. Clock Generator Functions
  54. Clock Generator Control Register
  55. System Clock Oscillators
  56. Examples of incorrect resonator connection
  57. Frequency divider
  58. Clock Generator Operation
  59. Changing Setting of CPU Clock
  67. CHAPTER 9 8-BIT TIMERS 30 AND 40
  68. Bit Timers 30, 40 Configuration
  69. Timer 30 Block Diagram
  70. Timer 40 Block Diagram
  71. Bit Timers 30, 40 Control Registers
  72. Format of 8-Bit Timer Mode Control Register 30
  73. Format of 8-Bit Timer Mode Control Register 40
  74. Format of Carrier Generator Output Control Register 40
  75. Format of Port Mode Register 2
  76. Bit Timers 30, 40 Operation
  77. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
  78. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
  79. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
  80. Timing of Operation of External Event Counter with 8-Bit Resolution
  81. Timing of Square-Wave Output with 8-Bit Resolution
  82. Operation as 16-bit timer counter
  83. Timing of Interval Timer Operation with 16-Bit Resolution
  84. Timing of External Event Counter Operation with 16-Bit Resolution
  85. Timing of Square-Wave Output with 16-Bit Resolution
  86. Operation as carrier generator
  87. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
  88. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
  89. Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
  90. Operation as PWM output (timer 40 only)
  91. PWM Output Mode Timing (Basic Operation)
  92. Notes on Using 8-Bit Timers 30, 40
  93. Counting Operation if Timer Is Started When TMI Is High
  94. CHAPTER 10 WATCHDOG TIMER
  95. Watchdog Timer Configuration
  96. Watchdog Timer Control Registers
  97. Format of Watchdog Timer Mode Register
  98. Watchdog Timer Operation
  99. Operation as interval timer
  100. CHAPTER 11 POWER-ON-CLEAR CIRCUITS
  101. Block Diagram of Power-on-Clear Circuit
  102. Power-on-Clear Circuit Control Registers
  103. Format of Low-Voltage Detection Register 1
  104. Power-on-Clear Circuit Operation
  105. Timing of Internal Reset Signal Generation When POC Circuit Normally Halted
  106. Operation of low-voltage detection (LVI) circuit
  107. LVI Circuit Operation Timing
  108. CHAPTER 12 BIT SEQUENTIAL BUFFER
  109. Bit Sequential Buffer Control Register
  110. Bit Sequential Buffer Operation
  111. CHAPTER 13 KEY RETURN CIRCUIT
  112. CHAPTER 14 INTERRUPT FUNCTIONS
  113. Interrupt Sources and Configuration
  114. Basic Configuration of Interrupt Function
  115. Interrupt Function Control Registers
  116. Format of Interrupt Mask Flag Register 0
  117. Interrupt Servicing Operation
  118. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT)
  119. Maskable interrupt request acknowledgment operation
  120. Interrupt Request Acknowledgment Processing Algorithm
  121. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution)
  122. Multiple interrupt servicing
  123. Interrupt request pending
  124. CHAPTER 15 STANDBY FUNCTION
  125. Standby function control register
  126. Standby Function Operation
  127. Releasing HALT Mode by Interrupt
  128. Releasing HALT Mode by RESET Input
  129. STOP mode
  130. Releasing STOP Mode by Interrupt
  131. Releasing STOP Mode by RESET Input
  132. CHAPTER 16 RESET FUNCTION
  133. Reset Timing by RESET Input
  134. Status of Hardware After Reset
  135. CHAPTER 17 µ PD78E9860A, 78E9861A
  136. EEPROM Features (Program Memory)
  137. Communication mode
  138. Example of Connection with Dedicated Flash Programmer
  139. Pin Connection List
  140. On-board pin processing
  141. Signal Conflict (Input Pin of Serial Interface)
  142. Signal Conflict (RESET Pin)
  143. Connection of adapter for EEPROM writing
  144. CHAPTER 18 MASK OPTIONS
  145. CHAPTER 19 INSTRUCTION SET OVERVIEW
  146. Description of "Operation" column
  147. Operation List
  148. Instructions Listed by Addressing Type
  149. CHAPTER 20 ELECTRICAL SPECIFICATIONS
  150. CHAPTER 22 PACKAGE DRAWING
  151. CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
  152. APPENDIX A DEVELOPMENT TOOLS
  153. A-1 Development Tools
  154. A.1 Software Package
  155. A.3 Control Software
  156. A.5 Debugging Tools (Hardware)
  157. A.6 Debugging Tools (Software)
  158. APPENDIX B NOTES ON TARGET SYSTEM DESIGN
  159. APPENDIX C REGISTER INDEX
  160. C.2 Register Symbol Index (in Alphabetical Order)
  161. APPENDIX D REVISION HISTORY
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