NEC ?PD703302 manuals
?PD703302
Table of contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- CHAPTER 1 INTRODUCTION
- K0/Kx1+, 78K0/Kx1 products lineup
- Features
- Applications
- Pin Configuration (Top View)
- Function Block Configuration
- Overview of Functions
- CHAPTER 2 PIN FUNCTIONS
- Pin I/O Circuits and Recommended Connection of Unused Pins
- Pin I/O Circuits
- CHAPTER 3 CPU FUNCTIONS
- CPU Register Set
- Program register set
- System register set
- Operating Modes
- Address Space
- Wraparound of CPU address space
- Memory map
- Areas
- Recommended use of address space
- Peripheral I/O registers
- Special registers
- Cautions
- CHAPTER 4 PORT FUNCTIONS
- Port Configuration
- Port 0
- Port 3
- Port 4
- Port 5
- Port 7
- Port 9
- Port CM
- Port DL
- Block Diagrams
- Port Register Setting When Alternate Function Is Used
- Hysteresis characteristics
- CHAPTER 5 CLOCK GENERATION FUNCTION
- Configuration
- Registers
- Operation
- PLL Function
- Usage
- CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
- Timer output operations
- Eliminating Noise on Capture Trigger Input Pin (TIP0a)
- CHAPTER 7 16-BIT TIMER/EVENT COUNTER 0
- Square wave output operation
- External event counter operation
- Operation in clear & start mode entered by TI010 pin valid edge input
- Free-running timer operation
- PPG output operation
- One-shot pulse output operation
- Pulse width measurement operation
- Special Use of TM01
- CHAPTER 8 8-BIT TIMER/EVENT COUNTER 5
- Operation as external event counter
- Square-wave output operation
- bit PWM output operation
- Operation as interval timer (16 bits)
- Operation as external event counter (16 bits)
- Square-wave output operation (16-bit resolution)
- CHAPTER 9 8-BIT TIMER H
- PWM output mode operation
- Carrier generator mode operation
- CHAPTER 10 INTERVAL TIMER, WATCH TIMER
- Watch Timer
- Register
- CHAPTER 11 WATCHDOG TIMER FUNCTIONS
- Watchdog Timer 2
- Function
- Security Function
- Overview
- Trigger modes
- Operation modes
- Power fail detection function
- Setting method
- How to Read A/D Converter Characteristics Table
- Interrupt Request Signals
- Transmit operation
- Continuous transmission operation
- Receive operation
- Reception error
- Parity types and corresponding operation
- Receive data noise filter
- SBF transmission/reception (UART0 only)
- Dedicated Baud Rate Generator n (BRGn)
- Serial clock generation
- Baud rate setting example
- Allowable baud rate range during reception
- Transfer rate during continuous transmission
- CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
- Single transfer mode
- Continuous transfer mode
- Output Pins
- Functions
- Start condition
- Addresses
- Stop condition
- Wait state
- Master device operation
- Slave device operation (when receiving slave address (match with address))
- Slave device operation (when receiving extension code)
- Operation without communication
- Operation when arbitration loss occurs (no communication after arbitration loss)
- Interrupt Request Signal (INTIIC0) Generation Timing and Wait Control
- Address Match Detection Method
- Extension Code
- Arbitration
- Wakeup Function
- Communication Reservation
- When communication reservation function is disabled (IICF0.IICRSV0 bit
- Communication Operations
- Master operation in single master system
- Master operation in multimaster system
- Slave operation
- Timing of Data Communication
- CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
- Non-Maskable Interrupts
- Restore
- NP flag
- Maskable Interrupts
- Priorities of maskable interrupts
- Interrupt control register (xxlCn)
- Interrupt mask registers 0, 1, 3 (IMR0, IMR1, IMR3)
- In-service priority register (ISPR)
- ID flag
- Watchdog timer mode register 1 (WDTM1)
- External Interrupt Request Input Pins (NMI, INTP0 to INTP7)
- Edge detection
- Software Exceptions
- EP flag
- Exception Trap
- Debug trap
- Multiple Interrupt Servicing Control
- Interrupt Response Time
- Periods in Which Interrupts Are Not Acknowledged by CPU
- CHAPTER 18 KEY INTERRUPT FUNCTION
- CHAPTER 19 STANDBY FUNCTION
- HALT Mode
- IDLE Mode
- STOP Mode
- Securing oscillation stabilization time when STOP mode is released
- Subclock Operation Mode
- Sub-IDLE Mode
- CHAPTER 20 RESET FUNCTION
- Register to Check Reset Source
- Reset Sources
- Reset operation by WDTRES1 signal
- Reset operation by WDTRES2 signal
- Power-on-clear reset operation
- Reset operation by low-voltage detector
- Reset operation by clock monitor
- Reset Output Function
- CHAPTER 21 CLOCK MONITOR
- Internal Oscillation Clock Operation Mode
- Internal Oscillation HALT Mode
- CHAPTER 22 LOW-VOLTAGE DETECTOR
- CHAPTER 23 POWER-ON-CLEAR CIRCUIT
- CHAPTER 24 ROM CORRECTION FUNCTION
- Control Registers
- Correction control register (CORCN)
- CHAPTER 25 MASK OPTION/OPTION BYTE
- Option Byte (Flash Memory Versions)
- CHAPTER 26 FLASH MEMORY
- Memory Configuration
- Functional Outline
- Rewriting by Dedicated Flash Programmer
- Communication mode
- Flash memory control
- Selection of communication mode
- Communication commands
- Pin connection
- Rewriting by Self Programming
- Standard self programming flow
- Flash functions
- Internal resources used
- ROM Security Function
- Setting
- CHAPTER 28 ELECTRICAL SPECIFICATIONS
- CHAPTER 29 PACKAGE DRAWINGS
- APPENDIX A DEVELOPMENT TOOLS
- A.1 Software Package
- A.4 Debugging Tools (Hardware)
- A.5 Debugging Tools (Software)
- A.6 Embedded Software
- APPENDIX B INSTRUCTION SET LIST
- B.2 Instruction Set (in Alphabetical Order)
- APPENDIX C REGISTER INDEX
- D.1 Major Revisions in This Edition
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