User’s Manual U14826EJ5V0UD 15LIST OF FIGURES (1/4)Figure No. Title Page3-1 Pin I/O Circuits................................................................................................................................................384-1 Memory Map (μPD789860, 789861)...............................................................................................................394-2 Memory Map (μPD78E9860A, 78E9861A) .....................................................................................................404-3 Data Memory Addressing (μPD789860, 789861) ...........................................................................................424-4 Data Memory Addressing (μPD78E9860A, 78E9861A)..................................................................................434-5 Program Counter Configuration ......................................................................................................................444-6 Program Status Word Configuration ...............................................................................................................444-7 Stack Pointer Configuration ............................................................................................................................454-8 Data to Be Saved to Stack Memory ................................................................................................................454-9 Data to Be Restored from Stack Memory .......................................................................................................454-10 General-Purpose Register Configuration ........................................................................................................465-1 EEPROM Block Diagram ................................................................................................................................585-2 Format of EEPROM Write Control Register 10 ...............................................................................................596-1 Block Diagram of P00 to P07 ..........................................................................................................................646-2 Block Diagram of P20 .....................................................................................................................................656-3 Block Diagram of P21 .....................................................................................................................................666-4 Block Diagram of P40 to P43 ..........................................................................................................................666-5 Format of Port Mode Register.........................................................................................................................677-1 Block Diagram of Clock Generator..................................................................................................................697-2 Format of Processor Clock Control Register...................................................................................................707-3 External Circuit of System Clock Oscillator.....................................................................................................717-4 Examples of Incorrect Resonator Connection.................................................................................................727-5 Switching Between System Clock and CPU Clock .........................................................................................758-1 Block Diagram of Clock Generator..................................................................................................................768-2 Format of Processor Clock Control Register...................................................................................................778-3 External Circuit of System Clock Oscillator.....................................................................................................788-4 Examples of Incorrect Resonator Connection.................................................................................................798-5 Switching Between System Clock and CPU Clock .........................................................................................829-1 Timer 30 Block Diagram .................................................................................................................................859-2 Timer 40 Block Diagram .................................................................................................................................869-3 Block Diagram of Output Controller (Timer 40) ...............................................................................................87
