NEC PD789860(A) manuals
PD789860(A)
Table of contents
- User's Manual U14826EJ5V0UD
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Features
- Quality Grade
- K/0S Series Lineup
- Block Diagram
- Overview of Functions
- Pin Configuration (Top View)
- CHAPTER 3 PIN FUNCTIONS
- Description of Pin Functions
- IC (mask ROM version only)
- Pin I/O Circuits and Recommended Connection of Unused Pins
- CHAPTER 4 CPU ARCHITECTURE
- Internal program memory space
- Special function register (SFR) area
- Processor Registers
- Stack Pointer Configuration
- General-purpose registers
- Special function registers (SFRs)
- Special Function Registers
- Instruction Address Addressing
- Immediate addressing
- Register addressing
- Operand Address Addressing
- Short direct addressing
- Special function register (SFR) addressing
- Register indirect addressing
- Based addressing
- CHAPTER 5 EEPROM (DATA MEMORY)
- Format of EEPROM Write Control Register 10
- Notes for EEPROM Writing
- CHAPTER 6 PORT FUNCTIONS
- Port 0
- Port 2
- Port 4
- Port Function Control Registers
- Operation of Port Functions
- Clock Generator Functions
- Clock Generator Control Register
- System Clock Oscillators
- Examples of incorrect resonator connection
- Frequency divider
- Clock Generator Operation
- Changing Setting of CPU Clock
- CHAPTER 9 8-BIT TIMERS 30 AND 40
- Bit Timers 30, 40 Configuration
- Timer 30 Block Diagram
- Timer 40 Block Diagram
- Bit Timers 30, 40 Control Registers
- Format of 8-Bit Timer Mode Control Register 30
- Format of 8-Bit Timer Mode Control Register 40
- Format of Carrier Generator Output Control Register 40
- Format of Port Mode Register 2
- Bit Timers 30, 40 Operation
- Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation)
- Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH)
- Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock)
- Timing of Operation of External Event Counter with 8-Bit Resolution
- Timing of Square-Wave Output with 8-Bit Resolution
- Operation as 16-bit timer counter
- Timing of Interval Timer Operation with 16-Bit Resolution
- Timing of External Event Counter Operation with 16-Bit Resolution
- Timing of Square-Wave Output with 16-Bit Resolution
- Operation as carrier generator
- Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N))
- Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N))
- Timing of Carrier Generator Operation (When CR40 = CRH40 = N)
- Operation as PWM output (timer 40 only)
- PWM Output Mode Timing (Basic Operation)
- Notes on Using 8-Bit Timers 30, 40
- Counting Operation if Timer Is Started When TMI Is High
- CHAPTER 10 WATCHDOG TIMER
- Watchdog Timer Configuration
- Watchdog Timer Control Registers
- Format of Watchdog Timer Mode Register
- Watchdog Timer Operation
- Operation as interval timer
- CHAPTER 11 POWER-ON-CLEAR CIRCUITS
- Block Diagram of Power-on-Clear Circuit
- Power-on-Clear Circuit Control Registers
- Format of Low-Voltage Detection Register 1
- Power-on-Clear Circuit Operation
- Timing of Internal Reset Signal Generation When POC Circuit Normally Halted
- Operation of low-voltage detection (LVI) circuit
- LVI Circuit Operation Timing
- CHAPTER 12 BIT SEQUENTIAL BUFFER
- Bit Sequential Buffer Control Register
- Bit Sequential Buffer Operation
- CHAPTER 13 KEY RETURN CIRCUIT
- CHAPTER 14 INTERRUPT FUNCTIONS
- Interrupt Sources and Configuration
- Basic Configuration of Interrupt Function
- Interrupt Function Control Registers
- Format of Interrupt Mask Flag Register 0
- Interrupt Servicing Operation
- Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment (INTWDT)
- Maskable interrupt request acknowledgment operation
- Interrupt Request Acknowledgment Processing Algorithm
- Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last Clock During Instruction Execution)
- Multiple interrupt servicing
- Interrupt request pending
- CHAPTER 15 STANDBY FUNCTION
- Standby function control register
- Standby Function Operation
- Releasing HALT Mode by Interrupt
- Releasing HALT Mode by RESET Input
- STOP mode
- Releasing STOP Mode by Interrupt
- Releasing STOP Mode by RESET Input
- CHAPTER 16 RESET FUNCTION
- Reset Timing by RESET Input
- Status of Hardware After Reset
- CHAPTER 17 µ PD78E9860A, 78E9861A
- EEPROM Features (Program Memory)
- Communication mode
- Example of Connection with Dedicated Flash Programmer
- Pin Connection List
- On-board pin processing
- Signal Conflict (Input Pin of Serial Interface)
- Signal Conflict (RESET Pin)
- Connection of adapter for EEPROM writing
- CHAPTER 18 MASK OPTIONS
- CHAPTER 19 INSTRUCTION SET OVERVIEW
- Description of "Operation" column
- Operation List
- Instructions Listed by Addressing Type
- CHAPTER 20 ELECTRICAL SPECIFICATIONS
- CHAPTER 22 PACKAGE DRAWING
- CHAPTER 23 RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A DEVELOPMENT TOOLS
- A-1 Development Tools
- A.1 Software Package
- A.3 Control Software
- A.5 Debugging Tools (Hardware)
- A.6 Debugging Tools (Software)
- APPENDIX B NOTES ON TARGET SYSTEM DESIGN
- APPENDIX C REGISTER INDEX
- C.2 Register Symbol Index (in Alphabetical Order)
- APPENDIX D REVISION HISTORY
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