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DDC Total-AceXtreme MIL-STD-1553 manuals

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Total-AceXtreme MIL-STD-1553

Brand: DDC | Category: Transceiver
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. PREFACE
  7. Technical Support
  8. OVERVIEW
  9. Figure 1. BU-67301B Total-AceXtreme
  10. Figure 2. Total-AceXtreme® Block Diagram
  11. Specifications
  12. Additional Support Documents
  13. Total-AceXtreme® Development Kit
  14. MIL-STD-1553 MODES AND ARCHITECTURE
  15. Figure 3. Bus Controller Block Diagram - Remote Terminal Operation
  16. Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation
  17. Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH)
  18. GLOBAL FEATURES
  19. DMA Controller
  20. BUILT-IN TEST
  21. Table 2. Supported JTAG Functions
  22. HOST INTERFACE
  23. Table 3. Total-AceXtreme® Host Interface Configuration Options
  24. Asynchronous Interface Mode
  25. Table 5. Asynchronous 16-bit Mode Configuration Options
  26. Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface
  27. Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface
  28. Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface
  29. Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface
  30. Table 6. Asynchronous Transfers
  31. Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing
  32. Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing
  33. Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing
  34. Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing
  35. Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing
  36. Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing
  37. Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing
  38. Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing
  39. Synchronous Host Processor Interface
  40. Table 8. Synchronous 16-bit Mode Configuration Options
  41. Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface
  42. Figure 20. 32-bit, Multiplexed Address, Synchronous Interface
  43. Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface
  44. Figure 22. 16-bit, Multiplexed Address, Synchronous Interface
  45. Table 9. Single-Word Synchronous Transfers
  46. Table 11. Synchronous Timing Parameters
  47. Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write Timing
  48. Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing
  49. Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing
  50. Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing
  51. Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing
  52. Timing
  53. PCI Interface
  54. Figure 48. Interface Between Host PCI Bus and Total-AceXtreme® - PCI Signal List
  55. Table 13. PCI Bus Interface Signals
  56. Table 14. PCI Timing Information
  57. Figure 49. PCI Parametric Timing
  58. Figure 51. PCI Slave Burst Read - PCI Initiator Timing
  59. Figure 52. PCI DMA Start Delay
  60. Figure 54. PCI DMA Burst Read
  61. POWER INPUTS
  62. Figure 56. Power-Up Initialization Sequence Timing
  63. MIL-STD-1553 TRANSCEIVER OPTIONS
  64. Using External Fiber Optic Transceivers
  65. Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers
  66. THERMAL MANAGEMENT FOR TOTAL-ACEXTREME
  67. REGISTER AND MEMORY ADDRESSING
  68. TOTAL-ACEXTREME® SIGNALS
  69. Table 16. JTAG Test
  70. Host Interface Signals
  71. Table 19. CPU Data Bus
  72. Table 20. RT Address Signals
  73. Table 22. Additional Connections & Interface to External Transceiver
  74. Table 23. MIL-STD-1553 Interface
  75. Table 25. No User Connections
  76. Pinout Table
  77. Total-AceXtreme® Pin Diagram
  78. MECHANICAL OUTLINE
  79. ORDERING INFORMATION
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