H O S T I N T E R F A C EData Device Corporation DS-BU-67301B-Gwww.ddc-web.com 1/14886.5 PCI InterfaceIn addition to the flexible parallel CPU interface, the Total-AceXtreme® also includesa PCI 2.3 compliant Target/Initiator interface. Table 12 lists the features andcharacteristics of the Total-AceXtreme’s PCI interface.Table 12. Total-AceXtreme® PCI Interface CharacteristicsPCI Characteristic/Feature Total-AceXtreme®PCI Specification Compliance Revision 2.3Maximum PCI clock frequency 66 MHzSupport 32-bit PCI Bus YESSupport 64-bit PCI Bus (AD[63::32]) NO3.3V Signaling YES5V Tolerant NOPCI Target Interface YESPCI Initiator Interface YESSingle-Channel PCI Initiator/DMA Engine Memory only, not registersPCI Initiator/DMA Engine: Transfer Directions Supports transfers in both directions: host-to-Total-AceXtreme and Total-AceXtreme -to-host.PCI Initiator/DMA Engine: Data Transfer Modes • Block transfer mode (single descriptor executionvia registers).• Scatter/gather mode (descriptors stored in hostmemory)PCI Initiator/DMA Engine: PCI burst lengths Programmable (including infinite)PCI Initiator/DMA Engine: PCI Retry timeout Programmable (including infinite)PCI Initiator/DMA Engine: Programmable Interrupts • DMA Complete• DMA Descriptor Done• DMA Abort Function via register controlMemory and Register Addressability • DWord or Word write accesses to memory• DWord write accesses to registers• DWord or Word read accesses from registers• No 8-bit accessesInterrupts supported INTA#PCI Retries SupportedDisconnect with Data SupportedTarget Abort Total-AceXtreme will never generate a target abortDelayed Transactions Supports up to two simultaneousBAR0/BAR1 Support BAR0 = Total-AceXtreme MemoryBAR1 = Total-AceXtreme RegistersZero wait state bursts Supported, for both reads and writes as both Targetand Initiator
