Data Device Corporation 108 DS-BU-67301B-Gwww.ddc-web.com 1/1411 TOTAL-ACEXTREME® SIGNALS11.1 Signal Descriptions and Pinout by Functional GroupsTable 15. Protocol ConfigurationSignal Name BALL Pullup/PulldownDescriptionDISABLE_BC (I) C14 50kPulldownWhen ‘1’, indicates that the Total-AceXtreme cannot operate in BC mode (i.e.BC operation is disabled).When ‘0’, indicates that the Total-AceXtreme can operate in BC modeprovided that it isn’t an RT-ONLY device.DISABLE_MULTI_RT (I) D14 50kPulldownWhen ‘1’, indicates that the Total-AceXtreme cannot operate in Multi-RTmode (i.e. Limited to one RT-Address).When ‘0’, indicates that the Total-AceXtreme can operate in Multi-RT mode.PCI_nCPU (I) C11 50kPulldownWhen ‘1’, indicates that the PCI interface is active. When ‘0’, indicates thatthe CPU Interface is active.nRTBOOT (I) D13 50k Pullup If nRTBOOT is connected to logic "0", the Total-AceXtreme will initialize inRT mode with the Busy status word bit set following power turn-on. IfnRTBOOT is hardwired to logic "1", the Total-AceXtreme will initialize ineither Idle mode (for an RT-only part), or BC mode (for a BC/RT/MT part).nPOR C10 None Power-on Reset. Asserting nPOR low resets all Total-AceXtreme logic, alongwith the PLL that generates the internal 160 MHz clock. Following the low-to-high transition of nPOR, if enabled (by DISABLE_BIST = ‘0’), the Total-AceXtreme will initiate its internal built-in self-test (BIST). The host processorshould not attempt to access the Total-AceXtreme registers or memory untilat least 1 ms after the low-to-high transition of nPOR. Following nPOR beingasserted high, the host processor must wait a minimum of 1 ms ifDISABLE_BIST = ‘0’, or 500 μs if DISABLE_BIST =’1' before accessingmemory or registers.PLL_LOCKED A13 None PLL Locked output. Indicates that the output from the PLL providing theinternal 160 MHz clock is operational. Immediately following power turn-on,PLL_LOCKED will assert low, and will remain low while nPOR is assertedlow. Assuming correct operation of the PLL, PLL_LOCKED will transitionfrom ‘0’ to ‘1’ following a maximum of 100 μs after nPOR goes high.
