H O S T I N T E R F A C EData Device Corporation DS-BU-67301B-Gwww.ddc-web.com 1/1465Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write TimingFigure 25 Notes:1. When nSELECT is asserted (low), the Total-AceXtreme® is selected for thisdata transfer. nSELECT must be asserted through the full transfer cycle, andde-asserted high at the end of the transfer.2. The CPU_WORD_EN[1:0] inputs are used to specify which 16-bit datamemory words are to be written. If either or both these bits is ‘0’, then thecorresponding 16-bit word(s) will not be written to Total-AceXtreme memory.These inputs should be tied high if unused. For register transfers, the value ofCPU_WORD_EN[1:0] must be ‘11’.3. Unless the Total-AceXtreme command FIFO is full, CPU_nSTOP is notasserted for memory accesses, and will remain high.nDATA_RDYCPU_DATACPU_WORD_EN[1:0]RD_nWRMEM_nREGCPU_ADDRnDATA_STRBnSELECTHOST_CLKCPU_nSTOPtDHtDStAStCLKAddresstRDD tRDDtSHtSStCS tCHDatatWaittAStAStAStAHtAHtAHtAHtSHCCPU_nLAST
