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Total-AceXtreme BU-67301B
DDC Total-AceXtreme MIL-STD-1553 Design Manual
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DDC Total-AceXtreme MIL-STD-1553 Design Manual
Table of content
Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
Table Of Contents
PREFACE
Technical Support
OVERVIEW
Figure 1. BU-67301B Total-AceXtreme
Figure 2. Total-AceXtreme® Block Diagram
Specifications
Additional Support Documents
Total-AceXtreme® Development Kit
MIL-STD-1553 MODES AND ARCHITECTURE
Figure 3. Bus Controller Block Diagram - Remote Terminal Operation
Figure 4. Remote Terminal Block Diagram - Monitor Mode Operation
Figure 5. Monitor Block Diagram - Advanced Data Handler (ADH)
GLOBAL FEATURES
DMA Controller
BUILT-IN TEST
Table 2. Supported JTAG Functions
HOST INTERFACE
Table 3. Total-AceXtreme® Host Interface Configuration Options
Asynchronous Interface Mode
Table 5. Asynchronous 16-bit Mode Configuration Options
Figure 7. 32-bit, Non-Multiplexed Address, Asynchronous Interface
Figure 8. 32-bit, Multiplexed Address, Asynchronous Interface
Figure 9. 16-bit, Non-Multiplexed Address, Asynchronous Interface
Figure 10. 16-bit, Multiplexed Address, Asynchronous Interface
Table 6. Asynchronous Transfers
Figure 11. Asynchronous Non-Multiplexed Address 32-bit Read Timing
Figure 12. Asynchronous Non-Multiplexed Address 32-bit Write Timing
Figure 13. Asynchronous Non-Multiplexed Address 16-bit Read Timing
Figure 14. Asynchronous Non-Multiplexed Address 16-bit Write Timing
Figure 15. Asynchronous Multiplexed Address 32-bit Read Timing
Figure 16. Asynchronous Multiplexed Address 32-bit Write Timing
Figure 17. Asynchronous Multiplexed Address 16-bit Read Timing
Figure 18. Asynchronous Multiplexed Address 16-bit Write Timing
Synchronous Host Processor Interface
Table 8. Synchronous 16-bit Mode Configuration Options
Figure 19. 32-bit, Non-Multiplexed Address, Synchronous Interface
Figure 20. 32-bit, Multiplexed Address, Synchronous Interface
Figure 21. 16-bit, Non-Multiplexed Address, Synchronous Interface
Figure 22. 16-bit, Multiplexed Address, Synchronous Interface
Table 9. Single-Word Synchronous Transfers
Table 11. Synchronous Timing Parameters
Figure 25. Synchronous, Non-Multiplexed Address - 32-bit Single-Word Write Timing
Figure 32. Synchronous, Multiplexed Address 32-bit Single-Word Write Timing
Figure 34. Synchronous, Multiplexed Address 16-bit Single-Word Register Read Timing
Figure 35. Synchronous, Multiplexed Address 16-bit Single-Word Memory Write Timing
Figure 36. Synchronous, Multiplexed Address 16-bit Single-Word Register Write Timing
Timing
PCI Interface
Figure 48. Interface Between Host PCI Bus and Total-AceXtreme® - PCI Signal List
Table 13. PCI Bus Interface Signals
Table 14. PCI Timing Information
Figure 49. PCI Parametric Timing
Figure 51. PCI Slave Burst Read - PCI Initiator Timing
Figure 52. PCI DMA Start Delay
Figure 54. PCI DMA Burst Read
POWER INPUTS
Figure 56. Power-Up Initialization Sequence Timing
MIL-STD-1553 TRANSCEIVER OPTIONS
Using External Fiber Optic Transceivers
Figure 60. Total-AceXtreme® Interface to Fiber Optic Transceivers
THERMAL MANAGEMENT FOR TOTAL-ACEXTREME
REGISTER AND MEMORY ADDRESSING
TOTAL-ACEXTREME® SIGNALS
Table 16. JTAG Test
Host Interface Signals
Table 19. CPU Data Bus
Table 20. RT Address Signals
Table 22. Additional Connections & Interface to External Transceiver
Table 23. MIL-STD-1553 Interface
Table 25. No User Connections
Pinout Table
Total-AceXtreme® Pin Diagram
MECHANICAL OUTLINE
ORDERING INFORMATION
M I L - S T D - 1 5 5 3
T R A N S C E I V E R
O P T I O N S
Data Device Corporation
DS-BU-67301B-G
www.ddc-web.com
1/14
103
Figure 60.
Total-AceXtreme®
Interface to Fiber Optic Transceivers
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