Contents - revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- ADMtek Inc
- chapter 1 product overview
- block diagram
- pin assignment
- Stream Cipher Scrambler/ De-scrambler
- Hashing Function
- Buffer Management
- VLAN
- Bandwidth control function
- Receive descriptors content
- USB 1.1 H OST C ONTROLLER
- DPLL
- Transfer Descriptor Format
- DMA operation
- function description
- chapter 4 register description
- S YSTEM AND I NTERRUPT R EGISTERS
- IRQ_raw_status, offset: 0x40
- FIQ_status, offset: 0x18
- S WITCH C ONTROL R EGISTER D ESCRIPTION
- SftReset, offset: 0x04
- PHY_St, offset: 0x14
- Mem_control, offset: 0x1c
- CPUp_conf, offset 0x24
- Port_conf1, offset 0x2c
- Reserved, offset: 0x34
- Reserved, offset: 0x3c
- ADDR_st0, offset 0x50
- BW_cntl0, offset 0x60
- PHY_cntl1, offset 0x6c
- PHY_cntl3, offset 0x80
- TOS_en, offset 0x8c
- PHY_cntl4, offset 0xA0
- Int_st, offset 0xB0
- Int_mask, offset 0xB4
- GPIO_conf0, offset 0xB8
- Swap_in, offset 0xC8
- receive_Lbaddr, offset 0xDc
- Timer, offset 0xF4
- port3_LED, offset 0x10c
- General Control , offset 0x00
- Interrupt Enable, offset 0x08
- Host General Control, offset 0x10
- SOF Frame number, offset 0x1C
- RH descriptor, offset 0x74
- Port x status, offset 0x78
- Host Descriptor Head Starting Address, offset 0x80
- MPMC Control register, offset 000h
- MPMC Config register, offset 008h
- MPMC Dynamic Refresh register, offset 024h
- MPMC Dynamic RAS register, offset 034h
- MPMC Dynamic RC register, offset 048h
- MPMC Static Extended Wait register, offset 080h
- MPMC Dynamic Ras Cas[0,1,2,3] register
- MPMC Static Wait Wen [0,1,2,3] register
- MPMC Static Wait Rd [0,1,2,3] register
- MPMC Static Wait Turn [0,1,2,3] register
- MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh
- MPMC PeriphID3 register, offset FECh
- MPMC PCellID1 register, offset FF4h
- UART receive status register/error clear register, offset 04h
- UART line control register, middle byte, offset 0ch
- UART flag register (UARTFR), offset 18h
- UARTIIR/UARTICR, offset 1ch
- A BSOLUTE M AXIMUM R ATINGS
- electrical specification
|
ADM5120 Function Description3.3 Switch Engine3.3.1 Hashing FunctionADM5120 provides an embedded 1K MAC address look-up table to implement theaddress recognition. The entry of hashing table is calculated by direct mapping or XORfunction to produce a 10-bit hashing address entry.3.3.2 Learning ProcessAddress learning process is composed of source address (SA) of packets and hashingfunction. ADM5120 will compare the SA of each incoming packet:a. If the source address of incoming packet is the same as the source MAC addresstable, then the aging status and port number will be updated.b. If the source address is different from the source MAC address table (mean addresscollision), then no learning process will occur.Exception cases of address learning:1. The packets have error2. The port learning is been disabled3. Address collision4. The source address is multicast5. The packets from CPU3.3.3 RoutingWhen a packet comes from portA, ADM5120 will compare its destination MAC addresswith the MAC address in the MAC address lookup table. If the address is the same andport number is portA means that the packet is a local packet, then it is discarded. If theaddress is the same but port numbers are different, the packet is a unicast packet, and willbe forwarded to the assigned port. If the incoming packet is a broadcasted one, amulticast one, or an unknown one (i.e. the destination address cannot be found in theMAC address lookup table), then the routing scheme will broadcast it to all ports.If the MAC address is VLAN address, then the packet will be routed to CPU port. TheVLAN address is programmed by CPU, but not from the address learning.3.3.4 ForwardingADMtek Inc. 3-4ADM5120 provides store-and-forward method as forwarding scheme. Each outgoingpacket, including to-CPU packets, will be stored in the buffer first, and then directly sentto the assigned port or CPU via DMA. However, only the good and non-local packetswill be sent.
PreviousNext |