Contents - revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- ADMtek Inc
- chapter 1 product overview
- block diagram
- pin assignment
- Stream Cipher Scrambler/ De-scrambler
- Hashing Function
- Buffer Management
- VLAN
- Bandwidth control function
- Receive descriptors content
- USB 1.1 H OST C ONTROLLER
- DPLL
- Transfer Descriptor Format
- DMA operation
- function description
- chapter 4 register description
- S YSTEM AND I NTERRUPT R EGISTERS
- IRQ_raw_status, offset: 0x40
- FIQ_status, offset: 0x18
- S WITCH C ONTROL R EGISTER D ESCRIPTION
- SftReset, offset: 0x04
- PHY_St, offset: 0x14
- Mem_control, offset: 0x1c
- CPUp_conf, offset 0x24
- Port_conf1, offset 0x2c
- Reserved, offset: 0x34
- Reserved, offset: 0x3c
- ADDR_st0, offset 0x50
- BW_cntl0, offset 0x60
- PHY_cntl1, offset 0x6c
- PHY_cntl3, offset 0x80
- TOS_en, offset 0x8c
- PHY_cntl4, offset 0xA0
- Int_st, offset 0xB0
- Int_mask, offset 0xB4
- GPIO_conf0, offset 0xB8
- Swap_in, offset 0xC8
- receive_Lbaddr, offset 0xDc
- Timer, offset 0xF4
- port3_LED, offset 0x10c
- General Control , offset 0x00
- Interrupt Enable, offset 0x08
- Host General Control, offset 0x10
- SOF Frame number, offset 0x1C
- RH descriptor, offset 0x74
- Port x status, offset 0x78
- Host Descriptor Head Starting Address, offset 0x80
- MPMC Control register, offset 000h
- MPMC Config register, offset 008h
- MPMC Dynamic Refresh register, offset 024h
- MPMC Dynamic RAS register, offset 034h
- MPMC Dynamic RC register, offset 048h
- MPMC Static Extended Wait register, offset 080h
- MPMC Dynamic Ras Cas[0,1,2,3] register
- MPMC Static Wait Wen [0,1,2,3] register
- MPMC Static Wait Rd [0,1,2,3] register
- MPMC Static Wait Turn [0,1,2,3] register
- MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh
- MPMC PeriphID3 register, offset FECh
- MPMC PCellID1 register, offset FF4h
- UART receive status register/error clear register, offset 04h
- UART line control register, middle byte, offset 0ch
- UART flag register (UARTFR), offset 18h
- UARTIIR/UARTICR, offset 1ch
- A BSOLUTE M AXIMUM R ATINGS
- electrical specification
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ADM5120 Register Description4.2.4 IRQ_raw_status, offset: 0x40Bits Type Name Description Initial value9:0 RO IRQ_raw_status[7:0]The status of the interrupt sources beforemasking.1: the corresponding IRQ is active031:10 RO Reserved Not Applicable 04.2.5 IRQ_enable, offset: 0x80Bits Type Name Description Initial value9:0 RW IRQ_enable[7:0] The enable register is used to mask theinterrupt source.1: enable the interrupt and allow theinterrupt request to MIPS.Writing “0” has no effect.031:10 RO Reserved Not Applicable 04.2.6 IRQ_enable_clear, offset: 0xc0Bits Type Name Description Initial value9:0 RW IRQ_enable_clear[7:0]The clear bits of the IRQ_enable.Writing “1” clear the corresponding bit ofIRQ_enable.Writing “0” has no effect.031:10 Reserved Not Applicable4.2.7 Reserved, offset: 0x10Bits Type Name Description Initial value31:0 Reserved Not Applicable4.2.8 INT_Mode, offset: 0x14ADMtek Inc. 4-2Bits Type Name Initial value9:0 RW INT_mode[9:0] The interrupt type of the interrupt sources.1: the corresponding Interrupt portgenerate the FIQ to MIPS0: the corresponding Interrupt portgenerate the IRQ to MIPS031:10 Reserved Not Applicable
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