Contents - revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- ADMtek Inc
- chapter 1 product overview
- block diagram
- pin assignment
- Stream Cipher Scrambler/ De-scrambler
- Hashing Function
- Buffer Management
- VLAN
- Bandwidth control function
- Receive descriptors content
- USB 1.1 H OST C ONTROLLER
- DPLL
- Transfer Descriptor Format
- DMA operation
- function description
- chapter 4 register description
- S YSTEM AND I NTERRUPT R EGISTERS
- IRQ_raw_status, offset: 0x40
- FIQ_status, offset: 0x18
- S WITCH C ONTROL R EGISTER D ESCRIPTION
- SftReset, offset: 0x04
- PHY_St, offset: 0x14
- Mem_control, offset: 0x1c
- CPUp_conf, offset 0x24
- Port_conf1, offset 0x2c
- Reserved, offset: 0x34
- Reserved, offset: 0x3c
- ADDR_st0, offset 0x50
- BW_cntl0, offset 0x60
- PHY_cntl1, offset 0x6c
- PHY_cntl3, offset 0x80
- TOS_en, offset 0x8c
- PHY_cntl4, offset 0xA0
- Int_st, offset 0xB0
- Int_mask, offset 0xB4
- GPIO_conf0, offset 0xB8
- Swap_in, offset 0xC8
- receive_Lbaddr, offset 0xDc
- Timer, offset 0xF4
- port3_LED, offset 0x10c
- General Control , offset 0x00
- Interrupt Enable, offset 0x08
- Host General Control, offset 0x10
- SOF Frame number, offset 0x1C
- RH descriptor, offset 0x74
- Port x status, offset 0x78
- Host Descriptor Head Starting Address, offset 0x80
- MPMC Control register, offset 000h
- MPMC Config register, offset 008h
- MPMC Dynamic Refresh register, offset 024h
- MPMC Dynamic RAS register, offset 034h
- MPMC Dynamic RC register, offset 048h
- MPMC Static Extended Wait register, offset 080h
- MPMC Dynamic Ras Cas[0,1,2,3] register
- MPMC Static Wait Wen [0,1,2,3] register
- MPMC Static Wait Rd [0,1,2,3] register
- MPMC Static Wait Turn [0,1,2,3] register
- MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh
- MPMC PeriphID3 register, offset FECh
- MPMC PCellID1 register, offset FF4h
- UART receive status register/error clear register, offset 04h
- UART line control register, middle byte, offset 0ch
- UART flag register (UARTFR), offset 18h
- UARTIIR/UARTICR, offset 1ch
- A BSOLUTE M AXIMUM R ATINGS
- electrical specification
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ADM5120 Register DescriptionIf VLAN type found, it will add 4-byte automatically31:24 Reserved Not Applicable4.4.41 PHY_cntl4, offset 0xA0Bits Name Description1:0 RO P0_cbbrk_length Port 0 cable broken length2 RO P0_cbbrk Port 0 cable broken3 Reserved Not Applicable5:4 RO P1_cbbrk_length Port 1 cable broken lengthRO P1_cbbrk Port 1 cable broken7 Reserved Not Applicable9:8 RO P2_cbbrk_length Port 2 cable broken length10 RO P2_cbbrk Port 2 cable broken11 Reserved Not Applicable13:12 RO P3_cbbrk_length Port 3 cable broken lengthRO P3_cbbrk Port 3 cable broken15 Reserved Not Applicable17:16 RO P4_cbbrk_length Port 4 cable broken length18 RO P4_cbbrk Port 4 cable broken19 Reserved Not Applicable20 RW volt23 1: 10BaseT voltage 2.3V, 0: 2.2V (default) 021 RW rom_code25 1: fix the ROM code to 2.5V, 0: 2.2V (default) 0Reserved Not ApplicableType Initial value61431:224.4.42 Empty_cnt, offset 0xA4Bits Type Name Description Initial value8:0 RO empty_cnt The empty block in the global buffer15:9 Reserved Not Applicable22:16 RO buffer_full_high The high-pri out-queue full ports23 Reserved Not Applicable30:24 RO buffer_full_low The low-pri out-queue full ports31 Reserved Not Applicable4.4.43 Port_cnt_sel, offset 0xA8Bits Type Name Description Initial valueRW port_sel The port selected for the port_cnt31:4 Reserved Not Applicable3:04.4.44 Port_cnt, offset 0xAcADMtek Inc. 4-19Bits Type Name Description Initial value
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