Contents - revision history
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- ADMtek Inc
- chapter 1 product overview
- block diagram
- pin assignment
- Stream Cipher Scrambler/ De-scrambler
- Hashing Function
- Buffer Management
- VLAN
- Bandwidth control function
- Receive descriptors content
- USB 1.1 H OST C ONTROLLER
- DPLL
- Transfer Descriptor Format
- DMA operation
- function description
- chapter 4 register description
- S YSTEM AND I NTERRUPT R EGISTERS
- IRQ_raw_status, offset: 0x40
- FIQ_status, offset: 0x18
- S WITCH C ONTROL R EGISTER D ESCRIPTION
- SftReset, offset: 0x04
- PHY_St, offset: 0x14
- Mem_control, offset: 0x1c
- CPUp_conf, offset 0x24
- Port_conf1, offset 0x2c
- Reserved, offset: 0x34
- Reserved, offset: 0x3c
- ADDR_st0, offset 0x50
- BW_cntl0, offset 0x60
- PHY_cntl1, offset 0x6c
- PHY_cntl3, offset 0x80
- TOS_en, offset 0x8c
- PHY_cntl4, offset 0xA0
- Int_st, offset 0xB0
- Int_mask, offset 0xB4
- GPIO_conf0, offset 0xB8
- Swap_in, offset 0xC8
- receive_Lbaddr, offset 0xDc
- Timer, offset 0xF4
- port3_LED, offset 0x10c
- General Control , offset 0x00
- Interrupt Enable, offset 0x08
- Host General Control, offset 0x10
- SOF Frame number, offset 0x1C
- RH descriptor, offset 0x74
- Port x status, offset 0x78
- Host Descriptor Head Starting Address, offset 0x80
- MPMC Control register, offset 000h
- MPMC Config register, offset 008h
- MPMC Dynamic Refresh register, offset 024h
- MPMC Dynamic RAS register, offset 034h
- MPMC Dynamic RC register, offset 048h
- MPMC Static Extended Wait register, offset 080h
- MPMC Dynamic Ras Cas[0,1,2,3] register
- MPMC Static Wait Wen [0,1,2,3] register
- MPMC Static Wait Rd [0,1,2,3] register
- MPMC Static Wait Turn [0,1,2,3] register
- MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh
- MPMC PeriphID3 register, offset FECh
- MPMC PCellID1 register, offset FF4h
- UART receive status register/error clear register, offset 04h
- UART line control register, middle byte, offset 0ch
- UART flag register (UARTFR), offset 18h
- UARTIIR/UARTICR, offset 1ch
- A BSOLUTE M AXIMUM R ATINGS
- electrical specification
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ADM5120 Register DescriptionBits Type Name Initial valueDescription31:28 RW Req_lat AHB request latency = the AHB bus request latency,4: 4 clocks latency between requests4.4.10 CPUp_conf, offset 0x24Bits Type Name Description Initial value0 RW DisCPUport Disable CPU port = 1: disable the switch CPU port, andso send packets to CPU and clear all the packets in theswitch buffer11 RW CRC_padding CRC padding from CPU = 1: the packet from CPU withCRC02 RW bridge mode bridge testing mode:0: default1: forward to CPU, if the DA is the port, belonged to theother VLAN (for the bridge mode testing)08:3 Reserved Not Applicable14:9 RW DisUN_port Disable unknown packets, from port(s), forward to CPU→ 1: no send unknown packet from the port0 to port5to CPU15 Reserved Not Applicable21:16 RW DisMC_port Disable multicast packets, from port(s), forward to CPU→ 1: no send MC from the port0 to port5 to CPU23:17 Reserved Not Applicable29:24 RW DisBC_port Disable broadcast packets, from port(s), forward to CPU→ 1: no send BC from the port0 to port5 to CPU31:30 RW Reserved Not Applicable4.4.11 Port_conf0, offset 0x28Bits Type Name Description Initial value5:0 RW Dis_port Disable port → 1: port disable (if dumb mode, default= 0)7:6 Reserved Not Applicable13:8 RW En_MC enable all MC packet broadcast to port in the sameVLAN (not including CPU) → 1: enable Layer2 MCbroadcast to ports, 0: do not broadcast MC15:14 Reserved Not Applicable21:16 RW En_BP Enable back pressure → 1: enable back pressure (butneed qualify BP_mode)ADMtek Inc. 4-10
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