ADMtek ADM5120 Datasheet
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Contents
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ADMtek Inc. V1.134.4.46 Int_mask, offset 0xB4 ............................................................................. 4-214.4.47 GPIO_conf0, offset 0xB8 ....................................................................... 4-224.4.48 GPIO_conf2, offset 0xBc ....................................................................... 4-224.4.49 Watchdog0, offset 0xC0 ......................................................................... 4-224.4.50 Watchdog1, offset 0xC4 ......................................................................... 4-224.4.51 Swap_in, offset 0xC8.............................................................................. 4-234.4.52 Swap_out, offset 0xCc............................................................................ 4-234.4.53 send_Hbaddr, offset 0xD0 ..................................................................... 4-234.4.54 send_Lbaddr, offset 0xD4 ...................................................................... 4-234.4.55 receive_Hbaddr, offset 0xD8 ................................................................. 4-234.4.56 receive_Lbaddr, offset 0xDc .................................................................. 4-244.4.57 send_Hwaddr, offset 0xE0 ..................................................................... 4-244.4.58 send_Lwaddr, offset 0xE4...................................................................... 4-244.4.59 receive_Hwaddr, offset 0xE8 ................................................................. 4-244.4.60 receive_Lwaddr, offset 0xEc.................................................................. 4-244.4.61 Timer_int, offset 0xF0............................................................................ 4-244.4.62 Timer, offset 0xF4 .................................................................................. 4-254.4.63 Reserved, offset 0xF8 ............................................................................. 4-254.4.64 Reserved, offset 0xFc ............................................................................. 4-254.4.65 port0_LED, offset 0x100........................................................................ 4-254.4.66 port1_LED, offset 0x104........................................................................ 4-254.4.67 port2_LED, offset 0x108........................................................................ 4-254.4.68 port3_LED, offset 0x10c ........................................................................ 4-264.4.69 port4_LED, offset 0x110........................................................................ 4-264.5 USB C ONTROL STATUS REGISTER M AP ............................................................. 4-264.6 USB C ONTROL STATUS REGISTERS DESCRIPTION.............................................. 4-274.6.1 General Control , offset 0x00................................................................. 4-274.6.2 Interrupt Status, offset 0x04................................................................... 4-274.6.3 Interrupt Enable, offset 0x08 ................................................................. 4-284.6.4 Reserved, offset 0x0C............................................................................. 4-284.6.5 Host General Control, offset 0x10 ......................................................... 4-294.6.6 Reserved, offset 0x14 ............................................................................. 4-294.6.7 SOF Frame interval, offset 0x18............................................................ 4-294.6.8 SOF Frame number, offset 0x1C ........................................................... 4-304.6.9 Reserved, offset 0x20 – 0x6C ................................................................. 4-304.6.10 Low speed threshold, offset 0x70 ........................................................... 4-304.6.11 RH descriptor, offset 0x74 ..................................................................... 4-314.6.12 Port x status, offset 0x78........................................................................ 4-334.6.13 Host Descriptor Head Starting Address, offset 0x80............................. 4-364.7 MPMC REGISTERS ............................................................................................. 4-364.7.1 MPMC Registers Summary.................................................................... 4-364.7.2 MPMC Control register, offset 000h ..................................................... 4-384.7.3 MPMC Status register, offset 004h........................................................ 4-384.7.4 MPMC Config register, offset 008h....................................................... 4-394.7.5 MPMC Dynamic Control register, offset 020h...................................... 4-39ADM5120 iv4.7.6 MPMC Dynamic Refresh register, offset 024h ...................................... 4-40 |
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